Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.

Abstract: An apparatus and method for generating pseudo-random test instructions for testing a microprocessor begins by providing an array of list structures (502 through 508). Each list structure (502 through 508) contains a list of instructions, a discipline field (34), a pick field (42) and a biasing field (36). A random list of instructions is created by using a list selection discipline field to determine which list (502 through 508) is selected. The discipline field in the particular list (502 through 508) is then used to determine a manner in which instructions are selected from a list of instructions contained within the list structure. The pick field indicates how many instructions are to be selected from each selected list structure using a method determined via the discipline field.

Abstract: A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The CLA* signal is an input to a primary master (10). The primary master (10) provides a base address external to the primary master (10) so that a slave device can access the base address. The CLA* signal is asserted by the slave device to signal that the base address is to be cycled in a bit-wise circular fashion to provide a plurality of addresses out from the primary master (10) wherein each address in the plurality is derived from the base address internal to the primary master (10). Typically four addresses are provided per base address via the internal control of the primary master (10) in response to three sequential assertions of the CLA* signal.

Abstract: An integrated circuit (10), which is designed using standard cells (20, 22, 24, 26, 28, 30, 32, 34, 35, 36, 37, 28, 40, 42, 44, 46, 48, 50, 52), usually has one or more empty spaces (54) wherein no circuitry is formed. These empty spaces may be used to form capacitor standard cells which have capacitors (see FIGS. 3 and 4) to both ground and power supply lines within the integrated circuit. These capacitors are used to reduce noise in the power and supply lines in a manner more useful/efficient than known methods. The capacitor standard cell taught herein is more useful/efficient due to the fact that the capacitance provided by these standard cells is distributed over the entire integrated circuit in small portions (i.e., standard cells are placed all over the integrated circuit (10)), and is placed close to the logic which is switching. It is the switching logic which is the root of a large portion of internal integrated circuit noise.

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A data processing system (10 or 28) and method uses a memory management unit (MMU 14). The processor has two privileged modes of operations, such as a user mode and a supervisor mode of operation. The MMU 14 has a first mode of operation wherein logical address translation is performed via cache accesses and tablewalks, and a second mode of operation. The second mode of operation involves providing translation attribute bits from one of either a first transparent translation register (TTR 16), a second transparent translation register (TTR 18), or a default location (22). The TTRs (16 and 18) can each map different address spaces and different addressed memory sizes and the default location (22) covers all memory that is not mapped by one of the TTRs (16 or 18). The default location (22) is programmable, provides write protection, and provides attribute bits independent from the privilege mode.

Abstract: A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18 resides in a client program 14 and never lose bits of precision by maintaining an internal data structure 16, which holds the data, and by manipulating that data by operators and methods which the program code 18 defines. The program code 18, which is embedded in a client program 14, comprises a method that uses "lazy" storage allocation for transparent data management for the arbitrary precision number in the internal data array 22, a "lazy" arithmetic evaluation for avoiding more costly arithmetic operations, a width method for an optimized significant bit calculation, and a method for efficient determining the number of trailing zeros method for more efficient IEEE floating point math emulation operations.

Abstract: An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=.DELTA.speed/.DELTA.area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area.

Abstract: A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

Abstract: A program (818) utilizes a functional description of a data processor to verify that the operations requested by the user are valid in the current context of the development environment (10). The program performs each of these functions by checking both physical (820) and contextual rules (838) stored in a memory (9). The program ensures that registers and memory in the data processor cannot be illegally configured and, therefore, fewer programming errors will occur during the development stages of a new data processing system.

Abstract: A test vector system (157) and method for generating and verifying test vectors for testing integrated circuit speed paths involves accessing a circuit model (160), a list of circuit paths (162) and a test vector verifier (165). A single circuit path, referred to as a selected path, is selected from the paths (162). Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are used as input to the test vector verifier. The test verifier produces patterns that provide robust delay path fault tests for the given path. The test patterns are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: In a multi-processing system (10), a cache controller is implemented to efficiently process collisions which occur when a predetermined address location in a data memory (26) is simultaneously accessed by two processors (20, 21). The cache controller is formed by both a cache control logic circuit (34) and a tag unit (36). In the tag unit (36), a snoop tag cache (40) and a data tag cache (42) respectively indicate whether a snooped value or an accessed data value is stored in data memory (26). A status bit array (41) provides status information for both tag caches (40, 42). By configuring the array (41) to store status information for both snoop and data tag caches (40, 42), status information is "forwarded" between tag caches (40, 42) when a collision occurs. Additionally, the cache controller modifies the timing of each of the accesses such that the status information may be "forwarded" more easily. The timing modification is also referred to as "resource pipelining.

Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems. In addition, all contact pads are formed within the periphery of the ICs but no contact pads are formed over active circuitry so that yield is improved.

Abstract: A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.

Abstract: A branch cache (40) has a plurality of storage levels (120, 122, 140, and/or 142) wherein at least two write registers (114 and 116) are used to perform a parallel write operation to at least two of the storage levels in the plurality of storage levels (120, 122, 140, and/or 142). The two write registers (114 and 116) are provided due to the fact that the branch cache 40 is implemented as a multi-state (typically five state--see FIG. 5) branch prediction unit having instruction folding. Instruction folding, as taught herein, allows a branch instruction which is predicted as being taken to be executed along with an instruction that precedes the branch in execution flow. The instruction which directly precedes the branch in execution flow is usually the instruction which is used to "fold" the branch. Effectively, this instruction folding allows branches, which are predicted as being taken, to be executed in zero clock cycles.

Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162), and a set of logic value constraints are set for logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: A compiler and/or a compilation method is used to change or compile a plurality of instructions in memory from a form which is better understood by a human user to a form which is readily executed by a microprocessor. In doing this compilation, execution optimization is usually performed. A more efficient job of optimization (and therefore improved software performance) is achieved by correctly finding/identifying induction variables in code loops which may be used in the compiler's optimization routines. Induction variable properties can be found by constructing and analyzing an integer transfer matrix wherein the values of variables at the beginning of one execution of the loop are related functionally to the values of variables at the end of the one execution of the loop. This matrix can be effectively processed using eigenvalue processing using integer unimodular matrices to determine induction variable properties which were previously missed by prior methods, thereby improving performance.