Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

Abstract: A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), a second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The termination signals cannot usually be provided as a valid signal for every clock edge of the apparatus when the apparatus is operating at a high frequency. Therefore, within in the apparatus, the termination signals are not always sampled at every clock edge. Instead, there is at least one counter within the primary master (10) which delays the sampling of the termination bits for a predetermined number of clocks cycles to allow time for the termination signals to settle and become valid logic signals before sampling begins. The SAS* signal communicates, external to the primary master (10), whether the sampling of the termination bits is being performed, or the sampling of the termination bits is being suppressed.

Abstract: A method (FIGS. 12-16) and a data processing system (FIG. 4) are used to verify the correct operation of one or more tri-state multiplexers (FIG. 3) located in a circuit model (37). The tri-state multiplexer checker (38) accesses the circuit model (37) and identifies the tri-state multiplexer(s). Once identified these tri-state multiplexers are checked to ensure that: (1) no two or more select/control lines to a tri-state MUX are enabled at a critical point in time wherein tri-state MUX output line contention can occur (i.e. both a logic zero and a logic one are being driven to the MUX output); and (2) that at least one select/control line is enabled during all critical periods of time so that a high impedance (high-Z) state is not propagated incorrectly through the MUX. This checking/verification is performed in a cut-set manner which is iterative and very time efficient when compared to prior methods.

Abstract: A data processor and method are used to find log.sub.p (x) wherein p is a numerical base and x is a floating point value. The method begins by deriving a number y from the quantity x wherein the number y has a predetermined sign portion, a predetermined exponent portion, and the fraction portion f. The predetermined fraction portion f being a truncated portion of x. A logarithm to the predetermined base p of the number y is found by calculating:log.sub.p (y)=-log.sub.p (a)+log.sub.p (1+(ay-1))where the constant a is read from a memory table of constants indexed by an index i. Index i is calculated from y where the fraction portion f of y lies in the range of 1.ltoreq.y<2 and the position in this range determines index i. The log.sub.p (y), once determined, is used to find the log.sub.p (x) in an accurate manner as indicated in equation 16 herein.

Abstract: A low power mode of an integrated circuit (IC) 10 is tested via a test controller 50. The IC 10 is placed in a low power mode where a plurality of pins represented by the pins 82, 72, and 62 are isolated from the internal circuitry, such as CPU 30, via circuits 60, 70, and 80. It is difficult, if not impossible, to test the IC 10 when in a low power mode since all pins are isolated from external circuitry and all clocks are stopped. Therefore, in order to test the low power mode, the test controller 50 can be selectively taken-out of low power mode via a RESET IN signal while all other circuitry in the IC 10 remains in the isolated low power mode. Test controller 50 can then conduct logical low power internal testing of the IC 10 while it is in low power mode and isolated. This testing in done by communicating data via the DATA IN and DATA OUT pins in a serial scan chain manner.

Abstract: A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of operation. When in low power mode, the internal clock circuit isolates the CPU clock (18) from the internal clock (28) and pulls the internal clock (28) to a stable logic state to ensure that the CPU is not changing state and consuming power. The test controller (16) can be in a low power mode along with the CPU (14) or in a normal mode while the CPU (14) is in the low power mode via the test control signal (26). When the CPU is in low power mode and the controller (16) is in normal mode, the controller (16) tests the operation of the circuit (12) to logically ensure that handling of the clock (18) is proper when entering, maintaining and exiting the low power mode of operation.

Abstract: A data processor and method are used to find log.sub.p (x) wherein p is a numerical base and x is a floating point value. The method begins by deriving a number y from the quantity x wherein the number y has a predetermined sign portion, a predetermined exponent portion, and the fraction portion f, the predetermined fraction portion f being a truncated portion of x. A logarithm to the predetermined base p of the number y is found by calculating:log.sub.p (y)=-log.sub.p (a)+log.sub.p (1+(ay-1))where the constant a is read from a memory table of constants indexed by an index i. Index i is calculated from y where the fraction portion f of y lies in the range of 1.ltoreq.y<2 and the position in this range determines index i. The log.sub.p (y), once determined, is used to find the log.sub.p (x) in an accurate manner as indicated in equation 16 herein.

Abstract: An integrated circuit for use in fiber distributed data interface (FDDI) system has four elastic layer and buffer management (ELM) circuits (12, 14, 16, and 18) coupled through a crossbar switch (20). The crossbar switch (20) allows any of the ELM circuits (12, 14, 16, and 18) to be coupled to any other ELM circuit (12, 14, 16, or 18) or to one of three external buses for FDDI communication. By using a crossbar switch and four ELM devices on a single integrated circuit, FDDI performance is improved while system design is made easier and more flexible than previously possible. Cipher circuitry (22, 24, 26, and 28) is used to scramble and descramble data ingoing and outcoming from the ELM devices. Concentrators, workstations, local area networks (LANs), and the like may incorporate the circuit (10) to improve performance and flexibility.

Abstract: A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.

Abstract: A processor (50) is coupled to a plurality of peripherals (56 and 58) via an address bus (54) and a data bus (52). The peripherals (56 and 58) contain base address registers (BARs) (68 and 70). The peripherals (56 and 58) are either identical peripherals or similar peripherals wherein the BARs (68 and 70) are addressed via the same address within the system. In order to allow for each peripheral (56 and 58) to be written with a unique BAR value (in order to allow each peripheral to have a separate and distinct address space), the storage devices (64 and 66) are provided. When a data value is sent on the data bus (52) which has a set D0 bit and a cleared D1 bit, the device (64) is set to an asserted state and the device (66) is set to a deasserted state.

Abstract: A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: A bus protocol uses signals to designate a bus transfer termination (BTT*) and a bus grant relinquish (BGR*). The BTT* signal is an output which is asserted by a bus master which currently has ownership of a bus to indicate to other potential bus masters that a bus transfer is complete and that bus ownership may be transferred to another bus master. The BGR* signal is an input to a bus master. When BGR* is asserted, a bus arbiter/controller is informing the current bus master that the bus must be relinquished as soon as possible, after the deassertion of the Bus Grant signal, with no regard for locked sequences. If BGR* is deasserted, the bus arbiter is informing the current bus master that the bus can be relinquished at a time which is convenient for the current bus master. In general, BGR* is a bit which indicates the urgency of a pending bus ownership transfer.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162). A set of logic value constraints is set for custom logic blocks, through the use of Boolean differences, and a set of logic value constraints is set for standard logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified.

Abstract: A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.

Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Abstract: A method for scheduling asynchronous transfer mode (ATM) data cells for transmission in an ATM system uses a plurality of queues. The plurality of queues are separated into waiting queues of a lower priority and transmit queues of a higher priority. ATM tokens which identify one active channel a piece are positioned in the queues and rotated/shifted to new positions over time. As time progresses, ATM tokens are shifted/rotated from waiting queues of a lower priority to transfer queues of a higher priority wherein the tokens (and therefore specific ATM channels) are selected and ATM data cell(s) are transmitted in response to the selection. This queued/shifted selection process ensures that bandwidth requirements are adhered to in the ATM system. The selected tokens are eventually (after all needed ATM data cell(s) are transmitted for a single selection) re-scheduled to a queue of lower priority.

Abstract: An asynchronous transfer mode (ATM) system has a plurality of physical layers (24, 50, 52, and 26) coupled to one ATM layer (12) for communicating ATM data cells. In order to allow bi-directional communication, both the receive interface and the transmit interface of FIGS. 14 and 15 are coupled between the ATM layer and each physical (PHY) layer in the plurality of physical layers. In order to identify which physical layer of the plurality of physical layers is to either receive or transmit a data cell, a physical layer ID byte is transmitted along with the UTOPIA protocol multi-byte ATM data cell to address one physical layer in the plurality of physical layers.

Abstract: A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.

Abstract: A reference current source (38) and a matched reference transistor (40) are provided as part of a current limiting circuit, wherein the matched reference transistor (40) is scaled, electrically matched, and physically located in close proximity to an on-chip switching transistor (16) of a DC--DC converter. By serially coupling the reference current source (38) to the reference transistor (40), a reference signal (48), which is equal to the voltage across the reference transistor (40), is generated. The reference signal (48) is compared to the voltage across the switching transistor (16) while the switching transistor (16) is conducting. When the voltage across the switching transistor (16) exceeds that across reference transistor (40), the gate drive to the switching transistor (16) is disabled for the remainder of the current conductive phase.