Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract: A CVD diamond material, substantially free of voids, has an average crystallite size greater than about 15 microns, a maximum intensity of the diamond Raman peak in counts/sec divided by the intensity of photoluminescence at 1270 cm.sup.-1 greater than about 3, a Raman sp.sup.3 full width half maximum less than about 6 cm.sup.-1 and a diamond-to-graphite Raman ratio greater than about 25. The diamond material may also comprise carbon atoms with a C.sup.13 content less than 0.05 atomic %.

Abstract: A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage and a bit line.

Abstract: The present invention comprises an article formed for a plurality of diamond-coated fibers preformed into a desired shape. Each of the fibers has first surface regions in contact with immediately adjacent other ones of the fibers, and second surface regions spaced apart from the immediately adjacent other ones of said fibers to define boundaries of inter-fiber voids between the immediately adjacent ones of the fibers. The voids are infiltrated with high thermal conductivity CVD diamond material continuously coating the second surface regions of the fibers and comprising merged growth fronts from the second surface regions of individual immediately adjacent ones of the fibers into the inter-particle voids.

Abstract: A plurality of integrating photosensors is disposed in an array of rows and columns, with a given row select line connected to the gates of P-channel MOS transistors associated with that given row and a given column sense line connected to the drains of the P-channel MOS transistors associated with that given column. A sense amplifier is associated with each column. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input and a non-inverting input. The non-inverting input is connected to a source of reference voltage the inverting input is connected to a sense line. A P-channel balance transistor is connected between the inverting input and the output of the amplifying element and a capacitor is also connected between the inverting input and output of the amplifying element. A capacitor, preferably a varactor element, is connected between the output and the inverting input of the amplifying element.

Abstract: A diamond coated article, wherein the diamond has a thermal conductivity of at least 17 Wcm K.

Abstract: Method for consolidating diamond material, substantially free of voids, has an average crystallite size greater than about 15 microns, a maximum intensity of the diamond Raman peak in counts/sec divided by the intensity of photoluminescence at 1270 cm.sup.-1 greater than about 3, a Raman sp.sup.3 full width half maximum less than about 6 cm.sup.-1 and a diamond-to-graphite Raman ratio greater than about 25. The diamond material may also comprise carbon atoms with a C.sup.13 content less than 0.05 atomic %.

Abstract: A method for programming an antifuse of a selected technology type comprises the steps of (1) applying a preselected number of programming pulses to the antifuse at a voltage less than the maximum voltage at which antifuses of that selected technology type are known to program, (2) testing to see if the antifuse has been programmed, (3) increasing the programming voltage by a preselected increment and applying the preselected number of programming pulses to the antifuse if the antifuse has not been programmed, and (4) repeating steps (2) and (3) until the antifuse has been programmed. The antifuse may be identified as defective if it does not program after a selected number of attempts.

Abstract: A process for fabricating a metal-to-metal antifuse in a process sequence for forming a double layer metal interconnect structure includes the steps of forming and defining a first metal interconnect layer, forming and planarizing an inter-metal dielectric layer, forming an antifuse cell opening in the inter-metal dielectric layer, forming and defining an antifuse layer, forming metal-to-metal via holes in the inter-metal dielectric layer, and forming and defining a second metal interconnect layer.

Abstract: A high efficiency pumping scheme mode matches the TEMOO laser mode volume with a plurality of linearly spaced laser diode pumping sources positioned along a lateral side of a block of laser material. The cavity resonator within the block is configured in a tightly folded zig-zag configuration. Pump radiation from the diode pumping sources is collimated by an optical fiber and the fold angle is selected to mode match the pump radiation to the mode volume.A laser oscillator is followed by one or more cascaded amplifier stages including a block of laser material arranged in a tightly folded zig-zag configuration. Pump radiation from the diode pumping sources is collimated by an optical fiber and the fold angle is selected to mode match the pump radiation to the mode volume.

Abstract: The present invention is a method and apparatus for performing neighborhood processing operations on an n dimensional processing plane. In a simple, two dimensional, example, an M by N processing plane is successively scanned by rows. The output information from each row is presented on column lines. The analog data resulting from a fixed number of successive scans are temporarily held in a multi-stage analog buffer. A computing array is configured to perform the neighborhood operations or other limited co-operand operations on the shifted data. The computing array examines information from a slice made up of selected numbers of successive rows of the entire array, performs the operations on that portion, and provides a series of output signals representative of the result.

Abstract: The present invention comprises an article formed from a plurality of diamond particles and non-diamond particles compatible with diamond deposition preformed into a desired shape. Each of the particles has first surface regions in contact with immediately adjacent other ones of the particles, and second surface regions spaced apart from the immediately adjacent other ones of said particles to define boundaries of inter-particle voids between the immediately adjacent ones of the particles. The voids are infiltrated with high thermal conductivity CVD diamond material continuously coating the second surface regions of the particles and comprising merged growth fronts from the second surface regions of individual immediately adjacent ones of the particles into the inter-particle voids.

Abstract: Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath.

Abstract: A pullup circuit for use with plurality of N-Channel pulldown transistors connected to a bit line includes a P-channel MOS pullup transistor connected between the bit line and a voltage rail. An inverter is connected between the bit line and the drain of an N-Channel MOS transistor having its gate connected to the voltage rail and its source connected to the gate of the P-Channel MOS pullup transistor. A first P-Channel MOS transistor is connected between the voltage rail and the gate of the P-Channel MOS pullup transistor. A second P-Channel MOS transistor having its gate connected to ground is connected between the bit line and the gate of the first P-Channel MOS transistor. Four P-Channel MOS divider transistors are connected between the drain of the first P-Channel MOS transistor and ground. The gates of the P-Channel MOS divider transistors are connected together to ground. The P-Channel MOS pullup transistor and the N-Channel MOS pulldown transistors are large.

Abstract: A bipolar phototransistor comprises both an integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element.

Abstract: A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

Abstract: Apparatus for forcing a memory cell to a known state upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and the bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.

Abstract: A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output.

Abstract: A moving object classifier is integrated onto a single integrated circuit chip and includes a retina comprising a two-dimensional array of photosensors upon which the image of the object of interest is focused. A position classifier receives inputs from the retina and determines where in the retina the image of an object is located. An object classifier receives inputs from the portion of interest of the retina and computes the degree of membership of the image to each class to be classified and determines which class has the largest membership function. A scan controller controlled by the position classifier limits the object classifier data to the portion of the retinal image which contains the object. An interface controller interfaces the other elements on the integrated circuit chip with a microcontroller, which comprises a standard CPU, memory and input/output lines interfacing to the interface controller.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.