Abstract: An apparatus for page mode programming of an EEPROM cell array with false loading protection is disclosed. The system includes a flip-flop operatively connected to a bit line for storing information to be loaded into an EEPROM memory cell, and false loading protection circuitry operatively connected to the bit line for preventing the false loading of an erroneous signal into the flip-flop and/or an EEPROM cell.

Abstract: A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source.

Abstract: A mechanism is provided for maintaining an open door in a selected fixed position includes a hydraulic cylinder having first and second ends. One end of a shaft axially disposed in the cylinder, passes through a hydraulic seal at one end of the cylinder. A piston is axially disposed on the shaft near its other end, and includes o-rings for sealing it against the cylinder walls. The piston includes first and second axially-disposed bores. First and second discs, each including an aperture are axially mounted on the shaft in contact with the opposing faces of the piston and are positioned such that the aperture of each is substantially aligned with one of the bores and blocks the other bore. The discs are held against the faces of the piston with a predetermined amount of force.

Abstract: An integrating photosensor includes an NPN phototransistor having its collector connected to a source of positive voltage, a P-channel MOS transistor having its gate connected to row-select line, its source connected to the emitter of the phototransistor, and its drain connected to a column sense line. The NPN phototransistor has an intrinsic base-collector capacitance. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input and a non-inverting input. The non-inverting input is connected to a source of reference voltage the inverting input is connected to a sense line. A P-channel balance transistor is connected between the inverting input and the output of the amplifying element and a capacitor is also connected between the inverting input and output of the amplifying element. An exponential feedback element is connected between the output and the inverting input of the amplifying element.

Abstract: A circuit for isolating a first low-voltage circuit mode from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes a novel two input NAND gate having one input structure configured from high voltage devices connected to the second circuit node. The other input of the NAND gate is a control input for the isolation device and is connected to a low-voltage logic signal which is high when the signal from the high programming voltage node is to be passed through to the low-voltage node and low when the low-voltage node is to be isolated from the high programming voltage node. The output of the NAND gate is connected to the first low-voltage circuit node.

Abstract: A first linear voltage to current converter includes an MOS current source transistor with its gate connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A second linear voltage to current converter includes a bipolar current source transistor with its base connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A differential pair includes in each leg a bipolar current source transistor with its base connected to a source of fixed voltage feeding the source of an MOS follower transistor. A differential amplifer includes two circuit legs including these transistor circuits.

Abstract: A misalignment tolerant antifuse includes a lower electrode, bounded by a relatively thick first insulating layer, an upper electrode separated from the lower electrode by a second insulating layer having a thickness less than that of the first insulating layer, a pair of antifuse window regions in the second insulating layer, abutting the first insulating layer on opposite sides of the lower electrode, the insulating material in the window regions being thinner than the remainder of the second insulating layer, and an upper electrode disposed above the second insulating layer and lying over the pair of regions and at least a portion of the first insulating layer.

Abstract: In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related t

Abstract: An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.

Abstract: Processes are provided for consolidating diamond particles into a mechanically stable diamond mass, called a diamond ceramic. A compacted aggregation of diamond particles is subjected to low pressure PECVD conditions in the presence of atomic hydrogen, with or without a carbon source gas, whereby a mechanically stable diamond ceramic is formed substantially devoid of interstitial spaces.

Abstract: A segmented routing architecture includes three or more different interior segment lengths within all of the segmented tracks in a channel. Four or more different segment lengths of interior segments are present in a channel if the sole segment in each unsegmented track is considered, too. Two or more different segment lengths of interior segments exist within a single wiring track. Lengths of adjacent segments within a track are balanced with a ratio not exceeding about two. In any given channel, the average length of all the segments in each column is relatively low in the interior and increases substantially monotonically towards the ends of the channel.

Abstract: An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Abstract: A real-time, multiuser time-share, computer system is disclosed. The computer system is particularly adapted for running computer software written for individual personal computers, including software which requires the interactive exchange of high resolution computer graphics information. Data is transferred between the host computer and remote terminals over a very high speed serial data transmission line at a rate of, for example, 25 MHz. Fiber optic duplex cables connect a host controller with one or more remote terminals. One fiber optic cable carries the data from the host controller to the remote terminal and the other cable carries data from the remote terminal to the host controller. Specially dedicated, high speed, hardwired electronic logic, such as 74F series TTL hardwired logic, encodes the software commands, transfers the data over a serial data link, and decodes the data so that slower speed hardware may direct the data to the appropriate operating hardware.

Abstract: Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.

Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

Abstract: A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two-input logic gate of a second type having first and second data inputs.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Abstract: A fault tolerant memory and method for sensing is disclosed. A pair of memory cells each including a memory device and a select device are connected to a pair of bit lines. The bit lines are connected through select devices to a differential sense amplifier. Each pair of memory cells stores a single bit of data; the first memory cell stores the data bit and the second memory cell stores the compliment of the data bit. The memory cells are fabricated such that they exhibit three states; a first state in which they conduct current, a second state in which they do not conduct current, and a third, abnormal, state into which they fail wherein they conduct approximately half of the current which would be conducted in the first state.

Abstract: A process is provided for forming synthetic diamond by vapor deposition of a carbon gas source in the presence of atomic hydrogen on a substrate contained in a fluidized bed. The diamond may be overcoated by vapor deposition of a non-diamond material.