Abstract: A method and apparatus is provided for controlling the transmit power of an analog modem when the transmit power level does not match the desired transmit power level, thus conforming to FCC regulations on transmit power and/or eliminating non-linearities associated with higher than required power levels and loss of signal-to-noise ratio and concomitant at loss of data rate if the transmit power levels are less than that desired. In one embodiment, the power level at the analog modem is sensed to ascertain if it is not at the desired transmit power level, with adjustment being provided by transmitting the desired change in the transmit power level to the digital modem, whereupon mapping parameters are redefined by adjusting the number of equivalence classes, thus to adjust transmit power at analog modem.

Abstract: A truncated product partial canonical signed digit (PCSD) multiplier is disclosed for use in a finite impulse response (FIR) digital filter. Each multiplier quantity is coded as two non-zero signed digits in an 8-bit word. Each non-zero signed digit is recoded into a four bit nibble for application to the multiplier. Each partial product output of the multiplier is truncated from 16 to 11 bits. The multiplier operations are performed in the sequence shift right, truncate, one's complement, add partial products and, according to the output of a logic control circuit, add one into an appropriate order.

Abstract: An ion implantation apparatus includes an ion source, ion analyzer, ion acceleration means and ion deflection means interconnected in a sequential manner, but excludes a variable slit shutter as a means for attenuating the ion beam. A controllable source of inactive diluent gas is interconnected so as to provide a means for selecting the concentration of ions provided by the ion source to the ion analyzer.

Abstract: A process for fabricating a power IC structure which includes the following masking steps:1. CMOS P well mask2. JFET (short-channel implant) mask3. Field oxide growth mask4. Deep P+ mask5. Polysilicon mask6. DMOS P well mask7. n-/n+ mask8. Contact window mask9. Metalization mask10. Overglass mask.

Abstract: An arc gap for an integrated circuit on a surface of a substrate of semiconductor material includes a first conductive strip over and insulated from the substrate surface. A layer of an insulating material is over the first conductive strip and a second conductive strip is on the insulating layer. The insulating layer has an opening therethrough which exposes at least a portion of the first conductive strip. The second conductive strip extends to substantially the edge of the opening in the insulating layer so that the two conductive strips are exposed to each other through the opening. The two conductive strips may be portions of a metallization pattern for the integrated circuit.

Abstract: A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be "converted" into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established.

Abstract: The present invention sets forth an integrated circuit (IC) device wherein the IC chip includes peripheral circuits, such as input/output circuits, which are arranged non-perpendicular with respect to the rectangular shape of the active area of the IC. This structure permits positioning some of the terminal bond pads closely adjacent the corners of the chip without overlap of adjacent circuits.

Abstract: A PNP transistor and a current limiting resistor are formed in a single active region of an integrated circuit device. The resistor is arranged to limit current flow between the emitter and collector regions of the transistor upon breakdown of the PN junctions due to momentary high voltage.

Abstract: An improved process for forming multilayer resist structures for lithographic processing of a substrate having topographical features is provided. The structures are comprised of a resist layer having thereover a layer of poly(vinyl pyrrolidone). When the resist layer is a photoresist, the subject structures may optionally contain an absorptive layer directly overlying the substrate and/or a layer of contrast enhancement material overlying the planarizing layer. The poly(vinyl pyrrolidone) optionally contains from about 0.05 to about 0.1 percent by weight of a suitable surfactant, suitably a nonionic surfactant.

Abstract: A varistor having a plurality of spaced electrodes positioned on common surface thereof and a conductive layer positioned on the opposed major surface thereof.

Abstract: A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

Abstract: The memory cell is a five transistor cell formed with complementary symmetry metal oxide (CMOS) semiconductor insulated gate field effect transistors (IGFETs) in the silicon-on-sapphire (SOS) technology with doped polycrystalline interconnects using buried contacts. Diodes are formed where doped polycrystalline silicon lines form buried contacts to underlying silicon epitaxial regions of opposite conductivity type and where silicon epitaxial regions of opposite conductivity type contact one another. The presence of these diodes has been shown by the inventor to not be detrimental to the operation of the memory cell.

Abstract: A low resistance silicon conductor for tunnelling under an intervening metal conductor on a semiconductor device is provided. The low resistance conductor includes two layers of highly doped single crystalline or polycrystalline silicon which are stacked so that one is directly over the other. A pair of metal conductors are arranged, one on each side of the intervening metal conductor. Each of the pair of metal conductors is formed in ohmic contact with a portion of each of the two layers of silicon near one of their adjacent edges, thereby forming a two layer conductive tunnel under the intervening metal conductor.

Abstract: A plurality of first cavities is formed in the planar surface of a silicon substrate. A first oxide region of predetermined thickness is formed in each of the first cavities such that each of the first oxide regions has a surface which is coplanar with the substrate surface. A layer of monocrystalline silicon is then epitaxially deposited over the planar first oxide region/substrate surface. Second cavities are then formed through the monocrystalline silicon layer and into the substrate adjacent the first oxide regions, extending to a depth equal to approximately one-half that of the first oxide regions. The second cavities are then thermally oxidized so as to form second oxide regions therein, these second oxide regions being coplanar with the first oxide regions. Silicon is next epitaxially deposited on those portions of the monocrystalline silicon layer remaining on the first oxide regions so as to yield a continuous monocrystalline silicon sheet over the first and second oxide regions.

Abstract: A method for depositing monocrystalline silicon at a uniform rate onto a plurality of unequally sized monocrystalline nucleation sites comprises initially providing a substrate having an apertured oxide mask on a major surface thereof. The oxide mask includes a plurality of apertures each of which exposes a nucleation site on the substrate surface. The substrate is then exposed to a mixture of dichlorosilane and hydrogen chloride at 850.degree. C. and a pressure less than approximately 50 torr, for a predetermined time. This yields a monocrystalline silicon island extending from each nucleation site. Each of the islands has a substantially flat profile across the major surface thereof and all islands are equal in thickness.

Abstract: A printed circuit board assembly is disclosed which includes a printed circuit board having in situ molded members for mechanically securing electrical and mechanical components and the like to the printed circuit board. The printed circuit board is manufactured using a method wherein a printed circuit board is initially prepared with the required printed circuit patterns and with apertures for in situ molded members and for the leads of the electrical components. The required molded members are then molded in situ in specified apertures of the printed circuit board. The electrical components are thereafter mechanically secured in place with the in situ molded members and the leads of the components are connected to the contact pads of the printed circuit pattern.

Abstract: A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

Abstract: A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiated so as to yield crystal damage that is equivalent to or greater than that which would be produced by irradiating with 1 MeV neutrons at a fluence greater than approximately 10.sup.13 cm.sup.-2. The region is then annealed at a temperature of approximately 350.degree. to 450.degree. C. for approximately 15 minutes to one hour so as to yield a density of stable recombination centers correlating with the pinning centers that provides a stable minority carrier lifetime within the semiconductor region.

Abstract: A structure for measuring electrical and physical characteristics of a semiconductor region includes a semiconductor region having a first portion of width W.sub.1 and a second portion of width W.sub.2, wherein W.sub.1 is not equal to W.sub.2. First, second, third and fourth contact areas to the semiconductor region are disposed in seriatim such that the second portion of the semiconductor region extends between the third and fourth contact areas. A bonding pad is electrically connected to each of the contact areas for supplying current to predetermined pairs of the contact areas and for measuring the voltage across predetermined pairs of the contact areas.

Abstract: In accordance with the present invention a method for forming an insulating layer over a substrate surface comprises providing first and second raised portions extending from the substrate surface, the first and second portions extending distances X.sub.1 and X.sub.2 respectively, and X.sub.2 being greater than X.sub.1. An insulating layer of thickness T.sub.3 is deposited over the surface so as to conform to the topography of the substrate surface and raised portions and a flowable layer is then deposited over the insulating layer. The flowable layer is next flowed so as to yield a substantially planar surface and then thinned until that portion of the insulating layer that overlies the second portion is exposed. The flowable layer and the exposed surface of the insulating layer are then simultaneously thinned so as to remove a greater thickness of flowable layer than insulating layer. The thinning is stopped when that portion of the insulating layer that overlies the first portion is exposed.