Abstract: A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped.

Abstract: A MOSFET device comprises a semiconductor wafer which includes a drain region of first conductivity type contiguous with a wafer surface. A diffused body region of second conductivity type extends into the wafer from the wafer surface so as to form a body/drain PN junction which has a polygonally-shaped intercept at the wafer surface. A plurality of source regions of first conductivity type extends into the wafer from the wafer surface within the boundary of the body region. The source regions define a plurality of channel regions, a contact area, and at least one shunt region at the surface of the body region. Each shunt region extends from the contact area to one of the corners of the body/drain PN junction polygonal intercept. A source electrode contacts the body region contact area and each of the source regions adjacent thereto.

Abstract: An IGFET device includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body/drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source/body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body/drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions.

Abstract: A VDMOS device comprises a semiconductor wafer having a major surface with a first conductivity type drain region thereat. An array of second conductivity type body regions, spaced from each other by distance D, is diffused into the drain region from the first surface. The body regions each include a relatively high conductivity supplementary body region and a first conductivity type source region diffused therein from within the first surface boundary thereof. The spacing between each source region and the drain region defines a channel region at the first surface. A source electrode contacts the source and body regions and an insulated gate electrode overlies each channel region. A gate bond pad, in direct contact with the gate electrode, overlies a second conductivity type gate shield region and is insulated therefrom. The gate shield region is contiguous with the drain region and is spaced from the neighboring channel regions by distance D.

Abstract: A method for forming a CMOS FET structure includes the steps of forming an apertured insulating layer on a silicon substrate and epitaxially forming a monocrystalline silicon island of first conductivity type through an aperture therein. The exposed surface of the silicon island is then thermally oxidized and the portion of the insulating layer not covered by the oxide is removed. A monocrystalline silicon island of second conductivity type is then formed adjacent to the oxidized silicon island of first conductivity type.

Abstract: A method for substantially uniformly thinning a silicon layer comprises providing a silicon layer having a surface, oxidizing substantially all of the surface so as to transform a uniformly thick layer of silicon into oxide, and removing all the oxide so as to expose the silicon layer.

Abstract: A semiconductor device structure incorporates a semiconductor wafer having first and second opposing major surfaces and an edge. A first region of first conductivity type is contiguous with the second surface and includes an edge portion which is contiguous with the wafer edge at the first surface. A second region, of second conductivity type, extends into the wafer from the first surface so as to form a PN junction with the first region at a predetermined depth from the first surface. A third region, of second conductivity type, extends into the wafer from the first surface to a depth greater than the predetermined depth. The third region is disposed between and is contiguous with the second region and the edge portion of the first region. When the wafer is silicon the third region has an areal charge concentration of approximately 1 to 2.times.10.sup.12 cm.sup.-2.

Abstract: Monocrystalline silicon is deposited on first and second portions of a substrate, the first and second portions having substantially unequal dimensions. The method comprises subjecting the substrate to a silicon-source gas and a predetermined concentration of chloride at a predetermined temperature. The chloride concentration is selected so as to create a substantially equally thick monocrystalline silicon deposit on each of the substrate portions.

Abstract: A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Abstract: A monocrystalline silicon layer is formed on a mask layer on a semiconductor substrate. An apertured mask layer is disposed on the substrate, and an epitaxial layer is then grown by a two-step deposition/etching cycle. By repeating the deposition/etching cycle a predetermined number of times, monocrystalline silicon will be grown from the substrate surface, through the mask aperture, and over the mask layer.

Abstract: A CMOS device incorporates a plurality of interconnected vertical IGFETs on a substrate. An insulated gate electrode is located on the substrate surface and a pair of monocrystalline silicon regions extend from the substrate surface such that each of the monocrystalline silicon regions is contiguous with a portion of the insulated gate electrode. One of the monocrystalline regions has a body region of first conductivity type and the other monocrystalline region has a body region of second conductivity type. Both of the body regions are located with respect to the insulated gate electrode such that an inversion channel can selectively be created in one of the body regions by applying a predetermined voltage to the insulated gate electrode.

Abstract: A method for forming a layer of monocrystalline diamond cubic material on a mask comprises initially providing a substrate having a monocrystalline surface which is parallel to a {100}-type crystallographic plane. A mask is then formed on the substrate, the mask including at least two apertures and each aperture including an edge which is oriented between 8.degree. and 14.degree. from a particular <001> direction on the surface. The aperture edges are mutually parallel and in mutual opposition and the mask apertures each expose a monocrystalline surface portion of the substrate. The diamond cubic material is then epitaxially grown through the apertures and over the mask so as to form a monocrystalline layer of substantially uniform quality overlying the mask between the edges of the apertures.

Abstract: An integrated device which incorporates a plurality of interconnected vertical IGFETs on a single substrate is described. A monocrystalline silicon region extends from an area of the substrate surface and a plurality of insulated gate electrodes are disposed so as to be contiguous with the monocrystalline silicon region. Each of the insulated gate electrodes can be selectively biased with a predetermined voltage so as to create an inversion channel in a segment of the monocrystalline silicon region contiguous therewith.

Abstract: A monocrystalline silicon layer is formed on a mask layer on a semiconductor substrate. An apertured mask layer is disposed on the substrate, and an epitaxial layer is then grown by a two-step deposition/etching cycle. By repeating the deposition/etching cycle a predetermined number of times, monocrystalline silicon will be grown from the substrate surface, through the mask aperture, and over the mask layer.

Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Abstract: A vertical MOSFET device includes a major surface having an active, gate-controlled portion adjacent to an inactive portion. A gate-controlled perimeter channel is disposed at the boundary between the active and inactive portions.

Abstract: A vertical IGFET device is formed on a substrate which includes a monocrystalline silicon portion at a surface thereof. An apertured insulated gate electrode is disposed on the substrate surface such that an area of monocrystalline silicon is exposed through the aperture. An epitaxial silicon region extends from the substrate surface within the gate electrode aperture and is appropriately doped such that a predetermined voltage applied to the insulated gate electrode forms a channel region in the epitaxial region adjacent thereto. The vertical IGFET is fabricated by a self-aligned technique, wherein the insulated gate electrode includes a first, underlying insulating layer and a second, overlying insulating layer. The second insulating layer protects the gate electrode when the first insulating layer is defined.

Abstract: A plurality of wafers is serially disposed between a reactant gas inlet portion and an exhaust gas outlet portion of a deposition chamber. The reactant gas comprises a predetermined mixture of N.sub.2 O and SiH.sub.4, and a positive, monotonically decreasing temperature gradient is provided between the wafer closest to the inlet portion to the wafer closest to the outlet portion, such that the thickness and resistivity of the deposited SIPOS (semi-insulating polycrystalline silicon) are substantially similar on each wafer.

Abstract: An apertured mask layer is disposed on a substrate having a monocrystalline portion at a surface thereof. Essentially all edges of the mask apertures are parallel to a predetermined crystallographic direction. A monocrystalline layer is then deposited such that it grows within the mask apertures and over the mask in a direction perpendicular to the aperture edges.