Abstract: A monolithic voltage controlled oscillator is fabricated on a single semiconductor body. The oscillator includes an FET and a varactor diode interconnected such that a voltage applied across the varactor modulates the oscillating frequency of the FET output.

Abstract: A vertical MOSFET includes source and gate electrodes on a major semiconductor surface, and a drain electrode on an opposing semiconductor surface. A shield electrode is disposed in proximity to the gate electrode so as to minimize feedback capacitance between the gate electrode and drain region. Additionally, the shield electrode increases the level of space charge limited current that can be supported in the drain region, and minimizes current crowding in the device.

Abstract: A first compound semiconductor layer is epitaxially formed on a surface of a semi-insulating substrate. The first semiconductor layer is then removed and a second compound semiconductor layer is epitaxially formed on the substrate surface which is now exposed.

Abstract: The surface of a dielectric is exposed to gaseous WF.sub.6 and H.sub.2 at a temperature between approximately 500.degree. C. and 650.degree. C. This initiates the formation of tungsten islands on the dielectric surface without damaging the surface. An appropriate metallization layer is then deposited from the vapor phase onto the tungsten island covered dielectric surface.

Abstract: The electron mobility in an active layer on a semi-insulating substrate is enhanced by initially performing a high energy implantation of an element which is inert in the semi-insulating material. Donor ions are then implanted so as to form the active layer in that area of the substrate in which the high energy implantation was performed, and the substrate is annealed.

Abstract: A low conductivity, first conductivity type epitaxial layer is formed on a substrate of high conductivity, first conductivity type semiconductor material. Conductivity modifiers of second conductivity type are then implanted into the epitaxial layer so as to create a PN junction in the epitaxial layer. The substrate is next thinned, and conductivity modifiers of first conductivity type are implanted into the thinned surface so as to form a very high conductivity layer at the thinned surface.

Abstract: A MOSFET device having minimized parasitic bipolar effects comprises a substrate having a surface at which source and drain regions are spaced so as to define a channel portion in a body region. The channel portion is formed in a relatively low conductivity portion of the body region, the remainder of the body region being of higher conductivity. A gate overlies the channel portion, and a method for automatically aligning the gate to a grooved MOSFET is described.

Abstract: A monolithic integrated circuit incorporates a substrate of III-V material having an interconnection pattern disposed on a surface thereof. An epitaxial layer is grown on the substrate surface such that it overgrows the interconnection pattern, and a plurality of circuit elements, formed on the surface of the epitaxial layer, are interconnected by contacts which extend from the epitaxial layer surface to the underlying interconnection pattern.

Abstract: A monolithic integrated circuit comprises a substrate having first and second opposing major surfaces. A semiconductor device is at the first major surface, a circuit film pattern is on the second major surface, and means for interconnecting the device to the film pattern are provided. On the first surface, a metallization layer surrounds the device and has a thickness greater than the height of the device from the first surface. Additionally, an electrode extension projects from the device to a height substantially equal to the thickness of the metallization layer.

Abstract: A vertical MOSFET structure which includes a drain which comprises a high conductivity region and a low conductivity region. The high conductivity drain region is contoured so as to minimize the device turn-on resistance without degrading the device breakdown voltage.

Abstract: A fixture for use within an epitaxial deposition reactor includes a box adapted to receive a semiconductor substrate. The box is movable to a position of reactant gas flow within the reactor and it includes a porous cover. A stagnant mixture of reactant gases is maintained between the substrate and the cover while the box is within the zone of reactant gas flow.

Abstract: A vertical MOSFET device having source, body and drain regions, includes an anode region in series with the drain region. The source, body and drain regions have a first forward current gain and the anode, drain and body regions have a second forward current gain, such that the sum of the current gains is less than unity. The anode region provides minority carrier injection into the drain region, enhancing device performance in power applications.

Abstract: A circuit pattern is formed on a front side surface of a semiconductor wafer and an apertured photoresist pattern is formed over the circuit pattern. Via holes are then formed by laser irradiating the wafer at sites corresponding to the photoresist apertures. The back side surface of the wafer is next metallized and this surface is adhered to a plating block by means of an adhesive layer. Electrical connection between the substrate and plating block is then made, the via holes are electroplated, and the substrate is separated from the plating block and adhesive layer.

Abstract: A method for fabricating adjacent electrically conducting and insulating regions in a silicon film is described. A substantially insulating layer of oxygenated, N or P doped, non-single crystalline silicon film is first formed. The film is then selectively laser irradiated so as to form an irradiated portion which is substantially conducting.

Abstract: A monocrystalline semiconductor substrate is provided, and a thin film pattern is defined on a surface thereof. An epitaxial layer is then grown on the substrate surface such that it overgrows the thin film pattern a predetermined distance. That portion of the thin film not covered by the epitaxial layer is then removed.

Abstract: A vapor phase deposition apparatus includes a coaxially mounted reactor tube, jacketed assembly tube, bearing/plug assembly, and rod/substrate holder. Gas inlets are provided in the reactor tube, and assembly tube and a vent is provided on the jacketed portion of the assembly tube, such that a double counterflow gas pattern can be established in the apparatus. The apparatus permits controllable deposition cycle and it can be readily disassembled for periodic maintenance.

Abstract: A semiconductor power device comprises a semiconductor pellet having first and second opposing major surfaces, including, in series, emitter, base and collector regions of alternate conductivity type. The collector region is substantially planar and adjacent to the second surface, the base region is adjacent to the collector region and extends to the first surface, and the emitter region extends relatively deeply into the pellet from the first surface and is substantially surrounded by the base region. The emitter region substantially surrounds a substantially centrally located extension of the base region, this extension being of relatively high resistance and also terminating at the first surface. An emitter electrode contacts the emitter region and the base region extension, a collector electrode contacts the collector region, and a base electrode contacts the base region.

Abstract: An apertured mask is formed on a major surface of a semiconductor substrate, and a groove is generated in the semiconductor in an area exposed by the aperture. A layer of electrode material is then formed on the groove surface, the layer extending beyond the groove and onto the mask. The mask is then stripped, and those portions of the electrode material extending beyond the groove are removed.

Abstract: A semiconductor power device comprises a semiconductor pellet having first and second opposing major surfaces, including, in series, emitter, base and collector regions forming a PNP transistor. The collector region is substantially planar and adjacent to the second surface; the base region is adjacent to the collector region and extends to the first surface; and the emitter region extends into the pellet from the first surface such that it is substantially surrounded by the base region. The emitter region substantially surrounds a substantially centrally located extension of the base region which also terminates at the first surface. Emitter, base and collector electrodes are ohmically disposed on the respective semiconductor regions and a Schottky barrier contact is formed on the base region extension, the Schottky contact being connected to the emitter electrode.

Abstract: A planar semiconductor device having a cathode region surrounding an anode region is flip chip mounted to a conductor film circuit. An anode contact extends from the anode region and is bonded to a first portion of the conductor film circuit such that that portion of the cathode region which overlaps the first portion of the conductor film circuit is minimized. That portion of the cathode region distal from the anode region is relatively wide, and a relatively large area cathode contact extends from the cathode region and is bonded to a second portion of the conductor film circuit.