Abstract: A chemical washing system is presented including a chemical dispensing system. The chemical dispensing system includes a container for storing a liquid chemical, a dispensing unit coupled to the container for dispensing the liquid chemical, and a conduit for conveying the liquid chemical from the dispensing unit to a receptacle of a machine which uses the liquid chemical during normal operation. The container, the dispensing unit, and the receptacle may be enclosed within one or more service areas separate from a "user interface area" containing a portion of the machine with which a user interfaces during normal operation. In order to prevent airborne particulates and other contaminants within the one or more service areas from entering the user interface area, a positive air pressure differential is maintained between the user interface area and the one or more service areas. The chemical washing system includes a textile laundering appliance (e.g.

Abstract: A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.

Abstract: A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor.

Abstract: The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the second mask has a second lateral dimension less than a first lateral dimension of the first mask. The second mask is used to pattern a gate conductor from the conductive gate layer such that the gate conductor has an ultra narrow lateral dimension. Lightly doped drain impurity areas are formed self-aligned to sidewall surfaces of the gate conductor. Spacers are formed laterally adjacent the sidewall surfaces of the gate conductor, and source and drain impurity areas are formed self-aligned to sidewall surfaces of the spacers.

Abstract: An integrated circuit fabrication process is provided for implanting silicon into select areas of a refractory metal to reduce the consumption of silicon-based junctions underlying those select areas during salicide formation. The refractory metal is subjected to a heat cycle to form salicide upon the junctions and polycide upon the upper surface of a gate conductor positioned between the junctions. In response to being heated, the metal atoms readily react with implanted silicon atoms positioned proximate the metal atoms to form salicide. Once a metal atom has reacted with implanted silicon atoms, it is no longer available to react with silicon atoms of the junctions. However, not all of the metal atoms react with implanted silicon atoms, so some of the metal atoms are free to react with the silicon atoms of the junctions. Interdiffusion and reaction between those available metal atoms and those silicon atoms of the junctions occurs as a result of heating the semiconductor topography.

Abstract: An apparatus and method are presented for separating a stiffener member from a substrate of a flip chip integrated circuit package such that the substrate is not damaged. The apparatus includes a base plate for receiving an upper portion of the device package including the stiffener, and a hand tool for receiving a lower portion of the device package including the substrate. During use, the base plate engages the upper portion of the device package and the hand tool engages the lower portion. The hand tool is moved in relation to the base plate such that an adhesive layer joining the stiffener and substrate is broken (i.e., sheared), and the stiffener is separated from the substrate. As the adhesive layer is typically an amorphous polymer material which softens with increased temperature, the base plate is preferably heated prior to effecting the movement of the hand tool in relation to the base plate.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the source/drain areas are formed simultaneously with the lightly doped drain areas. A gate electrode including a high-K gate dielectric and a gate conductor is formed upon a semiconductor substrate. The high-K gate dielectric is then selectively narrowed relative to the gate conductor. The source/drain areas and lightly doped drain areas are formed using a single impurity implant without the need for sidewall spacers on the gate electrode. A metal silicide layer may be formed across upper surfaces of the gate conductor and source/drain areas, also without the need for sidewall spacers on the gate electrode.

Abstract: A textile drying system is presented which draws in a quantity of air from an external space substantially equal to a quantity of air exhausted to the external space. The textile drying system includes one or more textile drying appliances (i.e., dryers) and a single air handling unit. Each dryer has an air input port and an air output port. During use, the single air handling unit provides a first quantity of air from a space outside a room in which the one or more dryers are located to the air input port of each dryer. A second quantity of air is exhausted through the air output port of each dryer to the space outside the room, wherein the second quantity of air is substantially equal to the first quantity of air. As a result, the textile drying system does not draw air from, or provide air to, the room in which the textile drying system is located.

Abstract: A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate.

Abstract: A system and method for measuring ampoule liquid level are presented. A buoy is arranged entirely within and detached from the ampoule. The buoy contains enough matter having a density less than that of the liquid to maintain flotation of the buoy, and has an exterior surface formed from a non-reactive material. The buoy is further designed to not interfere with any inlet or outlet structures of the ampoule. At least one magnet is displaced within the buoy such that the magnet is located near the ampoule's interior wall when the buoy is arranged within the ampoule. At least one sensor strip is located along the height of and entirely outside of the ampoule's interior wall, and at least one electronic sensor, containing at least one magnetically actuated switch, is located within each sensor strip. The electronic sensor may also contain a visible indicator and/or a resistor. The electronic sensor may be electronically connected to at least one separate system.

Abstract: An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems.

Abstract: A method and apparatus are provided for obtaining molecular information about materials at a selected site on or in a semiconductor topography. In a preferred embodiment, the selected site is a defect from a defect map generated by an automated wafer inspection system. A sample stage and drive/alignment system are used to move the semiconductor topography such that a selected defect is aligned with the illumination provided by a radiation scattering measurement system. A Raman spectroscopy system may be used for the radiation scattering measurement. The intensity and frequency of inelastically scattered radiation from the vicinity of the selected defect is compared to standard spectra to determine the chemical composition and material phase of the region analyzed. The depth into the topography probed may be adjusted by changing the wavelength of radiation used in the Raman spectroscopy measurement.

Abstract: A method for forming a local interconnect coupled to an active area of a semiconductor substrate is provided. The method comprises etching a local interconnect trench into an interlevel dielectric horizontally above the substrate. A titanium layer may be deposited across the semiconductor topography. A TiN diffusion layer is advantageously CVD deposited across the exposed surfaces of the titanium layer. A plasma containing N.sub.2 and H.sub.2 ions is used to bombard the surface of the TiN layer. The resulting TiN layer is conformal and has a low resistivity. A tungsten fill material is then deposited upon the TiN layer to a level above the dielectric. The tungsten adheres well to the TiN layer and is substantially free of voids. The TiN and the tungsten may be removed down to level commensurate with the surface of the dielectric. In this manner a local interconnect is formed electrically coupled to the active area.

Abstract: A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal.

Abstract: An apparatus and method for clocking digital and analog circuits on a common substrate is provided. The apparatus and method serves to reduce digitally derived noise at select times during which the analog input signal is sampled. Analog sampling error is thereby reduced while, at the same time, the digital clocking signal maintains maximum frequency. Digitally derived noise is substantially eliminated near the latter portion of each sampling interval to ensure an accurate sampled value exists at the culmination of that interval. During the earlier portion of each sampling interval, digital clocking pulses are maintained at a high frequency so as to enhance processing speeds. It is determined that only the latter portion of each sample interval is critical to the reduction of sampling error. Furthermore, the digital clocking pulses occur a non-power-of-two factor to ensure tonal noise is not coupled into the analog circuit frequency band of interest.

Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

Abstract: An analog-to-digital converter is provided for producing digital signal representative of analog signals. Noise induced upon the digital signals can be substantially removed using a digital decimation filter. The decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate and performs filtering operations with minimal complexity. Preferably, the front-end portion includes at least one stage of filtering and more preferably at least two filter stages, each of which perform interpolation separate from decimation. According to one embodiment, the first stage of the front-end portion involves decimation and the latter stage or stages of that portion involves a combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream produced by, for example, a quantizer to a value which can be more easily manipulated by the back-end portion of the digital decimation filter.