Abstract: A semiconductor process in which a local interconnect, formed above a first transistor level, is connected to the first transistor level through a self-aligned and low resistivity contact structure. A semiconductor substrate is provided and a first transistor level formed on an upper surface of the semiconductor substrate. The first transistor level includes a first transistor. A local interconnect is then formed over the first transistor level. The local interconnect is vertically displaced above the first transistor level such that the local interconnect may traverse a gate of the first transistor without contacting the gate. A contact structure is then formed to connect the first source/drain structure of the first transistor with the local interconnect.

Abstract: The present invention proposes a method and apparatus for compensating for the spatial variation across the surface of a wafer in certain design parameters of semiconductor devices. The spatial variation in the design parameters is due to the spatial variation in some of the processes involved in the manufacturing of the devices upon the semiconductor wafer. Using metrology tools, the physical, chemical, and electrical parameters of the devices across the surface of the wafer are first measured and recorded. These device parameters include the certain design parameters that must remain within certain design limits or that are to be optimized. Examples of these design parameters for a transistor are the threshold voltage, the switching speed, and the current consumption. The spatial variation in the design parameters may be compensated by altering the doping profile across the wafer with some of the implantation steps.

Abstract: A transistor is provided with a gradually increasing source and drain arsenic doping profile in a lateral direction from the gate conductor sidewall surfaces. The very smooth doping profile ensures small electric fields at the channel-drain interface for the benefit of reducing hot-carrier effects. Such a doping profile may be achieved by performing the ion implantation through a non-conformal layer of spin-on glass. By controlling the viscosity of the SOG and its deposition speed, different meniscus shapes may be formed. The doping profile of the arsenic in the source and drain regions follows the profile of the upper surface of the SOG. Arsenic is advantageously used for both the lightly doped and heavily doped regions of the source/drain junctions. Arsenic has lower mobility compared to phosphorus and is better at maintaining its original doping profile in heating of the device during further processing.

Abstract: An input/output (I/O) buffer is presented which selectively provides resistive termination for a transmission line coupled to an input/output node. The I/O buffer includes the input/output node, a first output driver stage, a second output driver stage, a differential amplifier, and an input termination stage. The first output driver stage is enabled when resistive termination of the transmission line is not required (e.g., when an older bus standard is to be supported). The second output driver stage is enabled when resistive termination of the transmission line is required (e.g., when a higher performance bus is to be supported). The differential amplifier produces a logic high input signal when a voltage driven upon the input/output node by the transmission line is greater than a reference voltage, and produces a logic low input signal at the output terminal when the voltage driven upon the input/output node by the transmission line is less than the reference voltage.

Abstract: A driver circuit is presented for producing particular output voltage levels at high speeds using a current switching technique. The circuit employs driver transistors connected in series between switchable current sources. The driver transistors switch current within the current sources through a resistor coupled between an output of the driver circuit and a reference terminal voltage. Switching the current occurs in rapid fashion within an opened loop arrangement. The switchable current sources are configured so that current is present through the current sources whenever a corresponding driver transistor is turned on. Current through the current sources, as switched through the resistor separating the reference terminal voltage and the driver output, is regulated by a closed loop replica circuit. The replica circuit may include an opamp whose output operably produces the regulated current via feedback from the current path to an input of the opamp.

Abstract: A transistor and a method for making a transistor are described. Barrier species such as nitrogen may be introduced into a semiconductor substrate to form a barrier layer. A dielectric having a high dielectric constant, preferably a metal- and oxygen-bearing dielectric, may then be deposited upon the semiconductor substrate. The barrier layer preferably mitigates short channel effects and prevents dopant and/or metal atom migration into or out of the gate structure. The dielectric may be annealed in an oxygen-bearing atmosphere to passivate the dielectric material and to incorporate barrier species into the dielectric. Alternatively, the anneal may be performed in an inert atmosphere. Following deposition of a conductive gate material upon the dielectric, a gate conductor and gate dielectric may be patterned. Lightly doped drain impurity areas and/or source and drain impurity areas may then be formed in the semiconductor substrate.

Abstract: An improved clock generation circuit is provided for changing the phase of one signal relative to the phase of another signal. Both signals presented to the clock generation circuit transition at the same frequency. One or both of those signals are delayed by dissimilar amounts to skew the phase difference between the signal pairs and 90.degree.. A phase detector, or logic gate, determines a phase differential between the incoming signals. A charge pump and storage device maintain a voltage level commensurate with that difference. The stored voltage is then used to control a feedback loop coupled from the output of the detector to a current path which traverses a buffer coupled between an input signal and a phase compensated output signal. The current path receives current necessary to change both the rise and fall rates produced by the buffer. According to another embodiment, two feedback loops may be used for a corresponding pair of buffers.

Abstract: An integrated circuit, apparatus, and a method is provided for programming and reading manufacturing information upon non-volatile storage elements of the integrated circuit. The manufacturing information includes the particular processing recipe and layout of the integrated circuit, each recipe or layout indicative of a specific hardware revision. The storage elements may be programmed prior to assembling the integrated circuit within a semiconductor package, and the programmed elements are read prior to shipping the packaged integrated circuit to a customer. If the read hardware revision is not qualified for release, the product will be placed in a staging area and prevented from shipping to a customer or end user. Thus, the programmed hardware revision serves to gate product at test before shipping that product to a customer.

Abstract: An apparatus and method are presented for immersing an object in a liquid such that a lower surface of the object does not touch a bottom surface of a container. The apparatus includes a forceps for holding the object and a pin for limiting movement of the forceps in relation to the container. The forceps includes a pair of jaws having opposed surfaces used to grip the object. A hole dimensioned to receive the pin extends through the pair of oppose surfaces. The container is used to hold the liquid, and has an opening in an upper portion surrounded by a lip. The object is gripped between the opposed surfaces of the jaws, and the pin is inserted through the hole in the forceps. The forceps is positioned above the container, then lowered until the object enters the liquid and the pin contacts the lip of the container. The pin limits vertical downward movement of the forceps with respect to the container, preventing the lower surface of the object from touching the bottom surface of the container.

Abstract: A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom.

Abstract: An integrated circuit fabrication process is provided in which a metal salicide and a diffusion barrier are formed concurrently. This process includes doping regions of a silicon substrate which are spaced apart by a polysilicon gate conductor, thereby forming source/drain junctions within the substrate upper surface. Oxide spacers are located on opposite sidewall surfaces of the gate conductor. The resulting semiconductor topography is then placed within a chamber having a pressurized and heated nitrogen ambient. A metal, i.e., titanium is deposited upon the semiconductor topography, and then annealing of the metal occurs. The titanium metal reacts with silicon at interfaces not containing nitrogen atoms, i.e., exclusive of the oxide spacers, to form titanium salicide. Concurrent with this reaction is the formation of titanium nitride upon the titanium metal. Finally, aluminum is deposited upon the titanium nitride to complete metallization.

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply.

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another.

Abstract: A computer system is presented having a mechanism for re-configuring the size of a data bus which links memory and/or input/output devices, or which links those devices to an execution unit. The mechanism includes a microcontroller embodying an chip select unit and a bus interface unit. The chip select unit allows computer system initiation from an upper memory address space occupied by a ROM. Thereafter, middle and lower memory address spaces occupied by RAM can be accessed by either an 8-bit or a 16-bit data bus, that data bus being either separate from or multiplexed with an address bus. The size of RAM can be configured in accordance with the data bus size which accesses RAM. Input/output address space can also be adjusted depending upon the data bus size which accesses input/output peripherals.

Abstract: A computer-aided synthesis and verification tool is provided for modeling a digital device at a behavioral level and for synthesizing to a structural level utilizing user-defined attributes. The behavioral level is represented as a Data Dependency Graph (DDG) having a plurality of operations (shown as nodes) and operands (shown as arcs) which connect the nodes. Each operation or node is represented as a graphical icon, wherein the icon can have user-defined attributes associated with it. The attributes, nodes, and arcs are compiled and reduced to a Register Transfer Level (RTL) simulation model compatible with present VHDL and Verilog formats. Conversion from a behavioral model to an RTL model includes monitoring the internal states at rising clock edges and constructing states, events and event transistions (i.e., control path information) for each data value in the matrix of values within the data path.

Abstract: A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied.

Abstract: An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis which the gate conductor extends. The removed portions presents a partially retained region of lesser thickness than the fully retained region immediately adjacent thereto. An implant is then forwarded to the substrate adjacent and partially below the gate conductor. Only the partially retained portions allow a subset of the originally forwarded ions to pass into the substrate to form a lightly doped drain (LDD) between the channel and the drain. The partially retained region occurs only near the drain and not adjacent the source so that the LDD area is self-aligned between the edge of the conductor and a line of demarcation separating the fully retained portion and the partially retained portion.

Abstract: A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate.

Abstract: A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.