Patents Represented by Attorney Kevin T. Cuenot
  • Patent number: 8352229
    Abstract: A computer-implemented method of creating a simulation engine for simulating a circuit design can include receiving a source code contribution from a high level modeling system and receiving a simulation model specified in an interpretive language that specifies the circuit design. The source code contribution can be compiled together with the simulation model using a Just-In-Time compiler. A simulation engine, specified in native machine code, can be output as a single, integrated software component formed from the source code contribution and the simulation model.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: January 8, 2013
    Assignee: Xilinx, Inc.
    Inventors: Haibing Ma, Chi Bun Chan, Jingzhao Ou
  • Patent number: 8332786
    Abstract: Within a high level modeling system (HLMS) comprising a processor and a memory, a method can include executing a system template comprising a plurality of modules of an electronic system, wherein each module represents a hardware component of the electronic system and is specified in the form of an extendable, higher order function, and extending, during runtime, a first module of the plurality of modules with a first extension by binding, via the processor, the first extension to the first module. The plurality of modules comprising the first extension to the first module can be stored within the memory.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventors: Chi Bun Chan, Jingzhao Ou
  • Patent number: 8330501
    Abstract: A system for voltage buffering within an integrated circuit (IC). The system can include a first buffer having an input and an output. The first buffer can be configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the system. The system can include a second buffer having an input and an output. The input of the first buffer can be coupled to the input of the second buffer. The output of the first buffer can be coupled to the output of the second buffer. The second buffer can be configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the system. The system further can include a controller configured to selectively enable only the first buffer or the second buffer at any given time.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventors: Vikram Santurkar, Gautham S. Jami
  • Patent number: 8332788
    Abstract: A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventors: Jay T. Young, W. Story Leavesley, III
  • Patent number: 8330536
    Abstract: An offset cancellation circuit can include an amplifier having a negative input, a positive input, and a single-ended output, wherein the positive input is configured to receive a reference voltage. The circuit also can include a capacitor having a first terminal and a second terminal. The first terminal can be coupled to the negative input of the amplifier. The capacitor can be configured to sample the offset voltage of the amplifier. The second terminal of the capacitor can be selectively coupled to the output of the amplifier.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventor: Patrick J. Quinn
  • Patent number: 8327201
    Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 4, 2012
    Assignee: Xilinx, Inc.
    Inventor: Andrew W. Lai
  • Patent number: 8312409
    Abstract: A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: November 13, 2012
    Assignee: Xilinx, Inc.
    Inventors: Gitu Jain, Vinay Verma, Taneem Ahmed, Sandor S. Kalman, Sanjeev Kwatra, Christopher H. Kingsley, Jason H. Anderson, Satyaki Das
  • Patent number: 8311659
    Abstract: A method of analyzing integrated circuit (IC) product yield can include storing, within a memory of a system comprising a processor, parametric data from a manufacturing process of an IC and determining a measure of non-random variation for at least one parameter of the parametric data using a pattern detection technique. The processor can compare the measure of non-random variation to a randomness criteria and selectively output a notification indicating that variation in the parameter is non-random according to the comparison of the measure of non-random variation to the randomness criteria.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 13, 2012
    Assignee: Xilinx, Inc.
    Inventors: Cinti X. Chen, Joe W. Zhao
  • Patent number: 8311174
    Abstract: A method of processing data within a controller for a network can include, while frame lock is not established, detecting a first preamble and a second preamble within a data stream of the network (1210, 1235). Biphase units between the first preamble and the second preamble can be counted (1215). Frame lock can be acquired on the data stream responsive to determining that the first preamble and the second preamble are separated by a number of biphase units corresponding to a frame (1235). A synchronization signal indicating that frame lock has been acquired can be output responsive to acquiring frame lock on the data stream (1240).
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: November 13, 2012
    Assignee: Xilinx, Inc.
    Inventors: Robert Bellarmin Susai, Venkata Vamsi Krishna Dhanikonda
  • Patent number: 8302041
    Abstract: A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 30, 2012
    Assignee: Xilinx, Inc.
    Inventors: Vi Chi Chan, Tetse Jang, Kevin Chung, Taneem Ahmed, David Nguyen Van Mau, Mehrdad Parsa, Amit Singh
  • Patent number: 8271915
    Abstract: A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: September 18, 2012
    Assignee: Xilinx, Inc.
    Inventor: Gareth D. Edwards
  • Patent number: 8270235
    Abstract: A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: September 18, 2012
    Assignee: Xilinx, Inc.
    Inventors: Richard W. Swanson, Tao Pi
  • Patent number: 8270742
    Abstract: A method of compressing data can include forming at least one container by grouping calls of data according to at least one data element of each call. The method can include arranging, via the processor, calls of the at least one container into a plurality of segments according to a minimal coordinate set and extracting common coordinates corresponding to a first coordinate type from the plurality of segments. Coordinates of a second coordinate type of each segment of the at least one container can be replaced with a segment start coordinate and first distance information specifying the coordinates of the second coordinate type. The common coordinates of the at least one container can be replaced with a common start coordinate and second distance information.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 18, 2012
    Assignee: Xilinx, Inc.
    Inventor: Chong M. Lee
  • Patent number: 8266583
    Abstract: A computer-implemented method of developing a packet processing application can include receiving a user input specifying a first function and a second function and automatically generating a high level programming language description of the packet processing application including a packet data storage unit (605, 610, 615). Packet units can be stored within the packet data storage unit at locations determined according to the first function and the second function. The high level programming language description also can be stored (630).
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 11, 2012
    Assignee: Xilinx, Inc.
    Inventor: Gordon J. Brebner
  • Patent number: 8248883
    Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: August 21, 2012
    Assignee: Xilinx, Inc.
    Inventors: Ting Lu, Kam-Wing Li, Anatoly Belkin, Ahmad R. Ansari
  • Patent number: 8230377
    Abstract: A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Wei Mark Fang, Srinivasan Dasasathyan
  • Patent number: 8224638
    Abstract: A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: July 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Nabeel Shirazi, Chi Bun Chan, Bradley K. Fross, Shay Ping Seng, Jonathan B. Ballagh
  • Patent number: 8219977
    Abstract: A method of testing software can include maintaining a cache within at least one of a plurality of farm machines of a testing farm. Each cache can include at least one version of test ingredients. The method can also include receiving, within at least one selected farm machine, a request to perform a test involving a test version of the test ingredients and comparing the test version of the test ingredients with versions of the test ingredients stored within the cache of the selected farm machine. The method can also include selectively updating a version of the test ingredients stored within the cache of the selected farm machine according to the comparison.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventor: Jeffrey D. Stroomer
  • Patent number: 8218277
    Abstract: A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (Rsub) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rsub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Richard C. Li, James Karp
  • Patent number: 8219957
    Abstract: A method performed by a system comprising a processor and a memory can include performing a global placement of a circuit design for a target programmable integrated circuit (IC) and clustering the circuit design using a selected size of cluster regions according to control sets identified within the circuit design. The method further can include determining a legalized placement of the clustered circuit design by solving a minimum cost network flow problem for the selected size of the cluster regions and the target programmable IC and assigning components to sites of the target programmable IC according to the legalized placement. The circuit design specifying the legalized placement can be stored within the memory.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Dinesh D. Gaitonde, Steven Li