Abstract: A method of capturing trace data can include storing trace data from a circuit as entries within memory slots of a trace buffer. Responsive to detecting a first trigger event, a trigger bit and a time marker bit within a first trigger event entry are set, wherein the trigger bit and the time marker bit are correlated with the first trigger event. A capture region within the trace buffer having a defined range can be determined. A first time marker correlated with the time marker bit of the first trigger event entry can be stored. Content of the capture region from the trace buffer correlated time markers can be output.

Abstract: A computer-implemented method of circuit design can include receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system (305) and receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains (310). A feasibility result can be determined according to the clock frequency constraints and the cost function (315). The feasibility result can indicate whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint. The feasibility result can be output (315).

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A method of assigning a plurality of input/output (I/O) objects of a circuit design to banks of a programmable integrated circuit (IC) using integer linear programming can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate assignment of each of the plurality of I/O objects to banks of the programmable IC (125-184), and storing a linear function that depends upon the plurality of constraints and a plurality of cost metrics, wherein each cost metric imposes a penalty when a selected I/O object of the circuit design is assigned to a bank of the programmable IC that is different from a bank to which the selected I/O object is assigned within a reference solution that is infeasible (190).

Abstract: method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit design can be clustered by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed to minimize critical connections. The circuit design can be declustered to perform additional placer optimization tasks on the declustered circuit design.

Abstract: A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (610, 620). Pairs of nets in the circuit design that are adjacent can be identified (625). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (640, 645, 655, 660). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (675). The measure of bridge fault coverage can be output (680).

Abstract: A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third section are associated with entries of the fourth section and wherein an entry of the third section and an associated entry of the fourth section collectively specify complete translation look-aside buffer data. The dual-port BRAM also can include first and second address ports concurrently accessing at least one of the first, second, third, or fourth sections of the dual-port BRAM to locate a virtual address to be translated.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: A computer-implemented method of predicting timing characteristics within a semiconductor device can include determining configuration information for the semiconductor device and determining a measure of timing degradation for data signals of the semiconductor device according to the configuration information. The measure of timing degradation for the data signals can be output.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

Abstract: A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.

Abstract: A system for detecting power-on of a circuit block within an integrated circuit (IC). The system can include a latch including a latch output and an inverted latch output. The latch can be coupled to, and powered by, a power supply providing power to the circuit block within the IC. The system further can include an exclusive OR circuit. The exclusive OR circuit can include an input stage coupled to the latch output and the inverted latch output. The exclusive OR circuit generates an output signal indicating whether the circuit block is in a power-on state.

Abstract: A method of processing a logical netlist for implementing a circuit design within a programmable logic device includes identifying a dynamically reconfigurable module (DRM) including at least one port from the logical netlist and determining whether the port connects with function logic for a function of the DRM. If the port connects with function logic, logic is inferred that connects the function logic with logic that is external to the DRM. If the port does not connect with function logic, logic is inferred that connects the port of the DRM with logic that is external to the DRM according to an attribute associated with the port. The logical netlist is updated to specify the inferred logic.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: Disclosed is a recursive, direct digital synthesizer includes an accumulator module and a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module. The CORDIC module rotates a signal according to a desired rotation angle specified by the accumulator module. An automatic gain control module is coupled to the CORDIC module. The automatic gain control module can apply a level of gain to the rotated signal.

Abstract: An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

Abstract: A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.