Abstract: Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.

Abstract: A system for monitoring a device under test implemented within an integrated circuit (IC) can include at least one probe that detects a designated type of data transaction, where in response to detecting the designated type of data transaction, each probe outputs a single data transaction detection signal. The system also can include a data collector coupled to each probe, where the data collector stores an indication of each data transaction detection signal that is output by each probe. The data collector can be configured so that no value of any probed signal is stored.

Abstract: A method of tuning an input/output (I/O) interface of a circuit design for a selected programmable integrated circuit can include determining whether the I/O interface meets a timing requirement and when the I/O interface does not meet the timing requirement, automatically adjusting a first timing setting of the I/O interface of the circuit design. The method can include iteratively determining whether the I/O interface meets the timing requirement, and responsive to each iteration, adjusting the first timing setting. The circuit design, including the adjusted first timing setting, can be output.

Abstract: A system can include a bus proxy comprising a primary slave coupled to a processor via a bus. The bus proxy system can include a hardware co-simulation interface disposed within the programmable IC and coupled to the bus proxy. The hardware co-simulation interface can buffer simulation data from the bus proxy and the host processing system. The bus proxy can include a secondary slave executing with a host processing system that reads data from, and writes data to, the hardware co-simulation interface, and communicates with at least one high level modeling system (HLMS) block executing within the host processing system. The primary slave can exert a slave wait signal on the bus responsive to detecting a bus request from the processor specifying an address corresponding to the HLMS block within the host processing system.

Abstract: A system for protecting an integrated circuit (IC) from electrostatic discharge (ESD) events includes a sensing circuit that detects an occurrence of an ESD event on one of a plurality of power supply rails of the IC and, in response, outputs an alert signal identifying the occurrence of the ESD event. The system includes a driver circuit that, responsive to receiving the alert signal, outputs an enable signal, and a cascaded switch. The cascaded switch includes first and second gates disposed upon a channel located between a drain of the cascaded switch coupled to a first power supply rail and a source of the cascaded switch coupled to a second power supply rail. Each of the two gates receives the enable signal and, responsive to the enable signal, the cascaded switch closes to establish a coupling between the first power supply rail and the second power supply rail.

Abstract: A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.

Abstract: A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsive to achieving the steady state, storing a circuit operational state of the circuit instantiated within the IC, an operational state of the processor, and a state of an executable memory utilized by the processor. A second circuit design can be created and a second build of the operating system can be created that collectively specify the circuit operational state, the operational state of the processor, and a state of an executable memory. The second circuit design and the second build of the operating system can be stored in the memory.

Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

Abstract: A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (1130). The method can include, responsive to detecting the deadlock state, adjusting the at least one control bit within a current frame (1135). Adjusting the at least one control bit clears the deadlock state and generates a modified frame. The modified frame can be output to at least one node within the network (1140).

Abstract: A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. The first PNS library can be correlated with a first die of the IC. The second PNS library can be correlated with the second die of the IC. Via a processor, a circuit element can be defined within a circuit design implemented within the IC according to the PNS library correlated to the die in which the circuit element is located.

Abstract: A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).

Abstract: A computer-implemented method of predicting a clock period within an integrated circuit can include determining configuration information for the integrated circuit (1430, 1435, 1445) and determining at least one measure of directional shift for an edge of a pulse of a reference clock signal of the integrated circuit with reference to at least one other clock signal of the integrated circuit (1440, 1450, 1460). The measure of directional shift for the edge of the pulse of the reference clock signal can be output (1475).

Abstract: A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Abstract: The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module, and receiving a user input selecting a plurality of ports of the module for inclusion in an interface through which the module communicates with the circuit design. Responsive to a user input specifying an interface type, the interface type can be associated with the plurality of ports. The interface type can be associated with a port list including standardized ports. Individual ones of the plurality of ports can be automatically matched with standardized ports from the port list. A programmatic interface description specifying the interface for the module can be output.

Abstract: A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.

Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.

Abstract: Within a system comprising a processor and a memory, a method of creating a circuit design for implementation within an integrated circuit can include inserting a placeholder block into the circuit design, wherein the circuit design includes a circuit block comprising circuitry and a circuit block interface, and wherein the placeholder block is devoid of circuitry and, responsive to receiving a user input specifying a coupling between the placeholder block and the circuit block, automatically determining a plurality of attributes of the circuit block interface. The method can include automatically generating, according to the attributes and by the processor, a placeholder interface within the placeholder block, wherein the placeholder interface is complementary to the circuit block interface. The placeholder block can be stored within the memory.

Abstract: Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.