Abstract: A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

Abstract: A computer-implemented method of probing a design under test (DUT) instantiated within a programmable logic device (PLD) can include disabling a clock signal provided to the DUT (340) and generating a partial bitstream specifying a new probe for the DUT (335). The partial bitstream can be merged with configuration data read-back from the PLD to create an updated partial bitstream (360, 365, 370). The updated partial bitstream can be loaded into the PLD (375). The clock signal provided to the PLD can be started and the DUT can continue to operate (380, 385).

Abstract: A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Abstract: A method of circuit design for an integrated circuit (IC) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the according to, at least in part, the reliability measures. The circuit design for the can be routed using the selected routing resources.

Abstract: A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.

Abstract: A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.

Abstract: A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of CFBs of the circuit design, determining an edge weight for each edge. The CFBs can be initially placed and a distance between each pair of CFBs joined by an edge of the undirected graph can be calculated. The CFB placement can be annealed by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of CFBs joined by the edge. The cost function also can sum the products for each edge. The CFB placement can be stored.

Abstract: A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circuit design and storing power usage data, from the simulating, for each of a plurality of circuit elements of the low-level circuit design. The circuit elements can be correlated with the high-level blocks of the HLMS circuit design. A power query of a selected block of the HLMS circuit design can be received and a measure of power usage for the selected high-level block can be determined according to the power usage data for selected ones of the plurality of circuit elements correlated with the selected high-level block. The measure of power usage for the selected high-level block can be output.

Abstract: A computer-implemented method of specifying a circuit design within a high-level modeling system (HLMS) can include, responsive to a scripted user input, instantiating a first and a second block objects within a hardware description interface (HDI) that is communicatively linked with the HLMS and, responsive to instantiating the first and second block objects, creating and displaying, within the HLMS, first and second modeling blocks representing the first and second xBlock objects respectively. Responsive to instantiating, within the HDI, a signal object bound to an output port of the first block object and an input port of the second block object, a modeling line can be created and displayed within the HLMS visually linking an output of the first modeling block with an input of the second modeling block. The first modeling block, second modeling block, and modeling line can be stored as a description of the circuit design.

Abstract: A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

Abstract: A method of accessing a peripheral device can include determining whether the peripheral device is busy. The method can include selectively providing to a processor, according to whether the peripheral device is busy, either a driver or a program. The driver, when executed by the processor, causes the processor to offload the operation to the peripheral device. The program, when executed by the processor, causes the processor to perform the operation in lieu of the peripheral device performing the operation.

Abstract: A computer-implemented method of verifying isolation of a plurality of instances of a redundant module of a circuit design that is implemented within a single, programmable integrated circuit can include counting component failures needed to establish a connection between at least two different ones of the plurality of instances of the redundant module. The method can include determining whether each instance of the redundant module is isolated from each other instance of the redundant module according to the counting of component failures, and outputting an indication whether each of the plurality of instances of the redundant module is isolated.

Abstract: A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.

Abstract: Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having outputs coupled to enable inputs of the numerous DCI modules, where operating the IC in a test mode configures the control circuit to selectively couple a control signal to the enable terminals of the numerous DCI modules. One DCI module of the numerous DCI modules can be enabled at a time facilitating testing of the configurable impedances of the I/O terminals.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bus adapter further can be coupled to a memory map interface (135) through which at least one peripheral device communicates with the processor. Single word operations can be exchanged between the processor and the dual-bus adapter through the first communication channel. Burst transfer operations can be performed by exchanging signaling information between the processor and the dual-bus adapter over the first communication channel and exchanging data words between the processor and the dual-bus adapter through the second communication channel.

Abstract: A method of determining a factorization permutation for a natural number can include storing a canonical prime factor vector within memory of a system and storing a first basis vector within the memory. The method can include deriving a first count sequence, including a plurality of counts, from the first basis vector, wherein each count of the first count sequence is a child of the first basis vector. For each count of the first count sequence, a second basis vector can be output that is a child of the count, wherein each count of the first count sequence and child second basis vector specifies a factorization permutation of the natural number.

Abstract: A computer-based system for testing a circuit design for implementation within an integrated circuit device can include a design application (205) providing simulation instructions for testing a circuit design and a simulation driver (225) receiving the simulation instructions and translating the simulation instructions into control protocol instructions specifying operations of an integrated circuit control protocol. The system can include a simulation environment (240). The simulation environment can include a communication module (245) communicating with the simulation driver, a simulation cable driver (250) receiving the control protocol instructions from the simulation driver via the communication module, and a control module (255). The simulation cable driver further can translate the control protocol instructions into signaling information corresponding to the integrated circuit control protocol.