Abstract: Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.

Abstract: A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.

Abstract: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

Abstract: A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and, from a first application, invoking at least one plug-in software component configured to access the dependency management data for the circuit design. The method further can include identifying partitions of the circuit design that must be run during the incremental flow using the plug-in software component.

Abstract: A method of integrating a High-level Language (HLL) function with a Hardware Description Language (HDL) representation of a circuit design can include identifying an attribute of the HDL representation of the circuit design that is resolved at compile time and determining a value for the attribute using an HLL function when compiling the HDL representation of the circuit design.

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Abstract: A method of calculating power usage of a lookup table (LUT) implemented on a programmable logic device can include determining input power usage of the LUT and determining output power usage of the LUT. The method further can include determining internal power usage of the LUT. Data rates, LUT configuration, and node capacitance information can be used in determining input, output, and internal power. A measure of power usage for the entire LUT can be provided by summing the input power usage, the output power usage, and the internal power usage.

Abstract: A method, system, and apparatus relating to automatically reducing an amount of code necessary for reproducing errors within programming language code is presented. The method can include identifying optional nodes of a hierarchical tree of programming language code, wherein each node of the tree corresponds to a type of programming language construct. A target node can be selected from the optional nodes. The method further can include excluding the target node and any sub-nodes of the target node from the programming language code, and determining whether the programming language code passes at least one test case.

Abstract: A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.

Abstract: A method of placing a circuit design on a target device can include subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition separated by a design-cutline, and subdividing at least a portion of the target device into at least a first device-partition and a second device-partition separated by a device-cutline. The method can include determining a design-cutset corresponding to a design-cutline and calculating a measure of required wire-bandwidth for the device-cutline according to the design-cutset. The length of the design-cutline can be increased according to the measure of required wire-bandwidth, thereby altering the perimeter of the first device-partition and the perimeter of the second device-partition.

Abstract: A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.

Abstract: A method of generating a low-skew network for a circuit design can include routing connections between a source and a plurality of loads of the network, determining a delay for at least one routed connection, and accepting the routed connections if the delay of each routed connection is within a skew tolerance range.

Abstract: A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit design, wherein each configuration specifies relative positioning of a source and a load of a connection and an estimated delay for the connection. The method can include calculating a maximum allowable delay for each of the plurality of connections of the circuit design and determining that a connection selected from the plurality of connections is critical according to the N best configurations associated with the critical connection and the maximum delay of the critical connection. A configuration from the N best configurations associated with the critical connection can be selected. An RPM for the critical connection can be generated using the selected configuration.

Abstract: A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.

Abstract: A method of assigning input/output (I/O) objects of a circuit design to banks of a target device using integer linear programming can include assigning the I/O objects of the circuit design to I/O groups according to compatibility among the I/O objects, and establishing a plurality of relationships, comprising measures of bank capacity, regulating assignment of the I/O objects of I/O groups to banks of the target device. Each measure of bank capacity can indicate a maximum number of I/O objects from a selected I/O group that can be assigned to a selected bank of the target device. The method also can include determining whether a feasible solution exists for assignment of the I/O objects of the circuit design to banks of the target device by minimizing an object function while observing the plurality of relationships.

Abstract: A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.

Abstract: A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.

Abstract: A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.