Abstract: A method of startup for a phase-locked loop (PLL) can include, at initiation of the PLL, providing a reference voltage from a startup voltage source to an input of a voltage controlled oscillator (VCO) in the PLL, wherein the reference voltage is set to a predetermined minimum voltage. The reference voltage can be stepwise increased from the predetermined minimum voltage. A frequency of a reference signal input to the PLL can be compared with a frequency of a feedback signal originating from an output of the VCO of the PLL to determine a frequency differential as the reference voltage increases. A determination can be made as to whether a convergence criterion is met according to the frequency differential. While the convergence criterion is not met, the reference voltage can be increased. When the convergence criterion is met, the reference voltage provided by the startup voltage source can be replaced with a voltage generated by an operational voltage source.

Abstract: A static random access memory (SRAM) can include an array of memory cells, wherein each memory cell is coupled to one of a plurality of sense amplifiers through a bitline. The SRAM also can include replica bitline circuitry including a replica bitline coupled to a replica bitline amplifier. The replica bitline amplifier can provide a strobe signal to the plurality of sense amplifiers, wherein the replica bitline amplifier includes a feedback path. An SRAM also may include a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array can be turned off responsive to the signal.

Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.

Abstract: A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.

Abstract: A programmable logic device can include a logic core in low power mode, a source input/output (I/O) bank including at least one source I/O pin, wherein the source I/O bank operates in normal operating mode, and a destination I/O bank including at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode. The programmable logic device also can include a bypass routing bus coupled to the source I/O bank and the destination I/O bank, wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.

Abstract: A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory. At a second simulation clock cycle, the clock of the circuit design can be gated. The stored configuration data can be loaded into configuration memory of the programmable IC, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle. The clock of the circuit design can be advanced a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle.

Abstract: A buffer management system for a data processing system can include a plurality of tokens wherein each token is associated with one of a plurality of buffers, and a plurality of first-in-first-out (FIFO) memories. Each FIFO memory can be associated with a stage of the data processing system and is configured to store at least one of the tokens. The buffer management system also can include control logic configured to determine a state of one or more selected buffers and transfer the token associated with the selected buffer from a source FIFO memory to a target FIFO memory. The target FIFO memory can be selected according to the state of the selected buffer.

Abstract: A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.

Abstract: An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

Abstract: A computer-implemented method of balancing logic resource usage in a circuit design for a programmable logic device (PLD) can include determining that an assignment of elements of the circuit design to a first type of logic resource of the PLD is unbalanced compared to an assignment of elements of the circuit design to an alternate type of logic resource of the PLD. An Integer Linear Programming (ILP) formulation specifying a balanced assignment of elements to the first and alternate types of logic resources can be generated. A solution for the ILP formulation can be obtained. Selected elements of the circuit design can be re-mapped from the first type of logic resource to the alternate type of logic resource according to the solution of the ILP formulation and the circuit design specifying the re-mapped elements can be output.

Abstract: A method of automatically generating multithreaded datapaths from a circuit description can include identifying a plurality of process threads from a circuit description, wherein each process thread comprises at least one function, and representing each of the plurality of process threads as an order of operations graph including nodes that correspond to functions and edges that indicate dependencies between the functions. The method also can include identifying at least one conditional edge from the order of operations graphs. An updated circuit description can be generated that specifies a multiplexer for each conditional edge.

Abstract: A method of accessing, from a host application written in a first programming language, a subroutine written in a second programming language can include serializing input data expressed as an XTable formatted in a first programming language into a string representation of the input data. The method further can include de-serializing the string representation of the input data as an XTable formatted in the second programming language and executing the subroutine, wherein the XTable formatted in the second programming language is processed as input. Output data returned from the subroutine that is expressed as an XTable formatted in the second programming language can be serialized into a string representation of the output data. The string representation of the output data can be de-serialized into an XTable formatted in the first programming language.

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.

Abstract: A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of attributes can specify a condition that, when met within at least one memory from the list, causes a signal to be generated to the processor. A description of an event interface for the processor can be automatically created according to the plurality of attributes of the interrupt. The description of the event interface can be incorporated into a description of the circuit design.

Abstract: A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.

Abstract: A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.

Abstract: A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.