Patents Represented by Attorney Kim-Marie Vo
  • Patent number: 8021970
    Abstract: A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinmiao J. Shen, Cheong M. Hong, Sung-Taeg Kang, Marc A Rossow
  • Patent number: 8014457
    Abstract: A received signal having pilots is converted to a first signal in the frequency domain having the pilots. The pilots are extracted from the first signal to obtain extracted pilots to form a second signal. The second signal is used to provide a first estimate of a channel. The first estimate is converted to the time domain. Noise is removed from the first estimate in the time domain to provide a second estimate of the channel in the time domain. An autocorrelation of the channel in the frequency domain is determined using the second estimate of the channel. Extension signals are determined using the autocorrelation. The extension signals are appended to the first estimate of the channel to obtain a third estimate of the channel. The third estimate is used to provide a data signal in the frequency domain.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: September 6, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ahsan U. Aziz, Leo G. Dehner
  • Patent number: 7986006
    Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 26, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, James D. Burnett
  • Patent number: 7960814
    Abstract: A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 14, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Nhat Dinh Vo
  • Patent number: 7932145
    Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 26, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
  • Patent number: 7904869
    Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: March 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
  • Patent number: 7889523
    Abstract: A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (Vin) into an output voltage signal (Vout), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: February 15, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas D. Cook, Tahmina Akhter, Jeffrey C. Cunningham
  • Patent number: 7871886
    Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: January 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 7858505
    Abstract: A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode and a second current electrode. Each of the first current electrode and the second current electrode has at least two regions of differing metal composition. A metal layer is deposited overlying the gate electrode, the first current electrode and the second current electrode. The metal layer is annealed to form two Schottky junctions in each of the first current electrode and the second current electrode. The two Schottky junctions have differing barrier levels.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Patent number: 7858487
    Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith
  • Patent number: 7846803
    Abstract: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Vishal P. Trivedi
  • Patent number: 7843730
    Abstract: A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ronald J. Syzdek
  • Patent number: 7836283
    Abstract: A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zheng Xu, Suraj Bhaskaran, Richard G. Collins, Jason T. Nearing
  • Patent number: 7834466
    Abstract: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert J. Wenzel, Trung Q Duong, Ilan Lidsky
  • Patent number: 7833852
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Vishal P. Trivedi, Da Zhang
  • Patent number: 7825720
    Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Kenneth R. Burch, Charles E. Seaberg
  • Patent number: 7824988
    Abstract: A method includes forming a source, a drain, and a disposable gate (38) of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable gates of the first transistor and the second transistor; forming a photoresist layer over the first transistor and the second transistor; patterning the photoresist layer to expose a gate region of the first transistor and a gate region of the second transistor; and implanting the substrate under the gate region of the first transistor and under the gate region of the second transistor, wherein implanting the substrate under the gate region of the first transistor provides a permanent shorting region between the source and the drain of the first transistor, and wherein implanting the substrate under the gate region of the second transistor adjusts a threshold voltage of the second transistor.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander Hoefler, James D. Burnett, Lawrence N. Herr
  • Patent number: 7820485
    Abstract: A method of forming a semiconductor package includes forming a coating over a first device, attaching the first device to a substrate using an adhesive, encapsulating the first device using an encapsulant material, releasing the first device from the substrate using the adhesive, removing a portion of the encapsulant material that is over the first device to expose the coating, and removing the coating over the first device to expose a portion of the first device.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William H. Lytle
  • Patent number: 7821104
    Abstract: A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chu-Chung Lee, Min Ding, Kevin J. Hess, Peng Su
  • Patent number: 7811932
    Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott K. Pozder, Ritwik Chatterjee