Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. Each column of the array is located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials to each column, with isolation of results for each column. In one embodiment, the memory cells are devoid of floating gate devices and use a non-conductive charge storage layer to store charges. In another embodiment, the memory cells store charges in nanocrystals.

Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Abstract: A extreme ultraviolet (EUV) mask blank having a reflective stack formed by depositing repeated periods of a silicon layer, a first barrier layer, a molybdenum layer, and a second barrier layer using atomic layer deposition is discussed. Precursors using silane and hydrogen are used to form the silicon layer. The first and second barrier layers are preferably different thicknesses of the same material and can be formed using precursors including diborane and methane. In one embodiment, the molybdenum layer is formed using precursors including hydrogen and molybdenum pentachloride or molybdenum pentaiodide. An EUV mask used to pattern a photoresist layer to form an integrated circuit is manufactured from the EUV mask blank.

Abstract: A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Abstract: A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.

Abstract: Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

Abstract: The invention relates to a method for measuring a required feature of a thin layer (4) used in a polishing process that is carried out by a polish head by producing a localized temperature rise on the surface of the layer (4) by focusing a short pump laser pulse (11) on the surface of the layer, as to generate a sound wave (13) that propagates into the layer; repeated measuring the surface reflection properties of the layer, by passing a probe laser pulse (21) and focusing it on the surface of the layer and by monitoring the portion of the probe laser pulse that is reflected (22) by the surface, as to detect a change in surface reflection properties caused by a boundary echo (32) that is a reflected part of the sound wave (13); measuring the elapsed time between the generation of the sound wave and the change in surface reflection properties; and calculating the required layer feature. Furthermore the invention relates to a measuring apparatus, which is able to perform the above-mentioned method.

Abstract: An electronic component includes a substrate (110) and an airbridge (890) located over the substrate. The airbridge has at least a first layer and a second layer over the first layer. The airbridge is electrically conductive where the first layer of the airbridge is less resistive than the second layer of the airbridge.

Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.

Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

Abstract: An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: An apparatus (10) for wafer grinding includes sensors (38) and a spectral analyzer to perform a spectral analysis of light received by the sensors (38) during grinding of a semiconductor wafer (12). Based on the spectral analysis, the grinding process is stopped or the force applied to the semiconductor wafer is modified. This in situ monitoring decreases breakage and overheating of the semiconductor wafer (12).

Abstract: An arrangement for transferring a pattern from a mask (100) onto a wafer is provided. A product area (110) of the mask (100) is at least partly surrounded by a frame (112) having an alignment mark area (114). In order to avoid the need to produce a specific mask set for different alignment styles, the mask (100) and the frame (112) are designed as being separate units. Further, methods for transferring a pattern from a mask to a wafer are provided that employ a frame separated from a product area.

Abstract: A conveyor element (10) for conveying wafer receptacles between a conveyor (12) and a loading station (11) of a manufacturing system in the semiconductor industry has a lifting mechanism (13) to move the wafer receptacle from a first position of the conveyor (12) or the loading station (11) into a second position of the conveyor (12) or of the loading station (11) substantially in a vertical direction. Rollers (14) are provided to move the wafer receptacle from the second position of the conveyor (12) along a substantially horizontal direction to the second position of the loading station (11) or from the second position of the loading station (11) to the second position of the conveyor (12).

Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.