Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Abstract: A memory and a method for programming a memory device are discussed. The method comprises selecting a cell to program, wherein the cell is coupled to a bit line, applying a first programming pulse, wherein the first programming pulse comprises applying a first voltage to the bit line, verifying if the cell is programmed after applying the first programming pulse, and applying a second programming pulse to the bit line after applying the first programming pulse if the cell is not programmed after applying the first programming pulse, wherein second programming pulse comprises applying a second voltage to the bit line, wherein the second voltage is different than the first voltage.

Abstract: An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, and a transistor on the same semiconductor. The first semiconductor protective layer protects the semiconductor substrate during formation of the second semiconductor layer, and the second semiconductor layer protects the second semiconductor material during subsequent processing of the first semiconductor. In one embodiment, the first semiconductor includes silicon and the second semiconductor material includes germanium.

Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract: In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.

Abstract: In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate (12) by forming elevated sources and drains (56) in contact with extensions (46) within the top silicon layer (18) of the SOI substrate (12). Buried conductive regions (42) are formed within the top silicon layer (18) below the extensions (46) to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (56), extensions (46) and the buried conductive regions (42) in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (56), extensions (46) and the buried conductive regions (42).

Abstract: A dielectric layer comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor and a substrate. In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Abstract: A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the-insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).

Abstract: A method of assembling a semiconductor component includes providing a pedestal, placing a first piece on the curved pedestal, wherein the first piece comprises a semiconductor die, placing a second piece over the first piece, and providing an adhesive between the first piece and the second piece. The method further includes applying pressure with a first plate to the first piece and second piece to snap the first piece with the second piece, and applying heat with a second plate to reflow the adhesive, wherein applying heat is performed simultaneously with applying pressure.

Abstract: A bilayer hardmask 26 is used to manufacture a mask 10, which is can be implemented to pattern a resist 165 on a semiconductor wafer 150. In one embodiment, the bilayer hardmask 26 has two layers: a first hardmask layer 28 and a second hardmask layer 30. The first hardmask layer 28 may be carbon and can be etched selective to the overlying second hardmask layer 30 and an underlying absorber structure 20. In one embodiment, the second hardmask layer 30 is a transparent layer of SiON, SiN, or SiO2. The bilayer hardmask 26 allows for a thinner resist to be used during fabrication of the mask 10.

Abstract: A solder system includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier, applying the solder system to the carrier, coupling the terminal to the carrier via the solder system, melting the solder system to attach the terminal to the carrier and form a completed semiconductor device, and determining if the completed semiconductor device has a different predetermined property from the solder system.

Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (42, 64) over a mold encapsulant (35, 62). The conductive layer (42, 64) may be electrically coupled using a wire to the leadframe (10, 52) of the semiconductor package (2, 50). The electrical coupling can be performed by wire bonding two device portions (2, 4, 6, 8) of a leadframe (10) together and then cutting the wire bond (32) by forming a groove (40) in the overlying mold encapsulant (35) to form two wires (33). The conductive layer (42) is then electrically coupled to each of the two wires (33). In another embodiment, a looped wire bond (61) is formed on top of a semiconductor die (57). After mold encapsulation, portions of the mold encapsulant (62) are removed to expose portions of the looped wire bond (61).

Abstract: A novel device, such as a semiconductor device, a microfluidic device, a surface acoustic wave device an imprint template, or the like, including an amorphous carbon layer for improved adhesion of organic layers and method of fabrication. The device includes a substrate having a surface, an amorphous carbon layer, formed overlying the surface of the substrate, and a low surface energy material layer overlying the surface of the substrate. The device is formed by providing a substrate having a surface, depositing a low surface energy material layer and an amorphous carbon layer overlying the surface of the substrate adjacent the low surface energy material layer using plasma enhanced chemical vapor deposition (PECVD) or sputtering.

Abstract: To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

Abstract: An EUV mask (10) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. An etch stop layer (20) may be provided between a lower multilayer reflective stack (14) and an upper multilayer reflective stack (22) to ensure an appropriate and accurate depth of the opening. An absorber layer (32) may be deposited within the opening to sufficiently reduce the amount of reflection within dark region (30). Optimal thicknesses and locations of the various layers are described.

Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

Abstract: A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

Abstract: A top-most layer (64) is formed over a bond pad layer (62) and under a passivation layer (68) and a polyimide layer (72). Openings (70 and 74) are formed within the passivation layer (68) and the polyimide layer (72) to expose the top-most layer (64), which protects the bond pad layer (62) during the formation of the openings (70 and 74). In one embodiment, the exposed top-most layer (64) is selectively etched using hydrogen peroxide and an amine, such as ammonium hydroxide. Because the chemistry does not attack the bond pad layer (62), the bond pad layer's thickness is not decreased and thus, reliability of the bond pad is maintained.