Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.

Abstract: A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.

Abstract: A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.

Abstract: A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.

Abstract: A computer system includes a service partition, not directly accessible to a user, having a security agent to inspect data entering and exiting the computer system on a virtual private network (VPN) tunnel, and a service partition VPN unit to communicate with a VPN gateway. The computer system also includes a user partition, accessible to a user, having a user partition VPN unit to initiate construction of the VPN tunnel with the VPN gateway. Other embodiments are described and claimed.

Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.

Abstract: A method for managing simulation includes modifying a design for a system to allow for a path pulse filter to filter a pathpulse delay, on a signal transmitted to a component, that is greater than an IOpath delay.

Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Abstract: A method for compressing trace data includes maintaining a record of register values known to a debugger unit. A data packet is generated that includes a value in response to determining that the debugger unit is unable to determine the value from the register values known to the debugger unit.

Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.

Abstract: A method for designing a system on a target device is disclosed. A first plurality of components in the system are assigned to be placed by an computer aided design (CAD) tool based on a criterion. A second plurality of components in the system are assigned to be placed by a hardware placement unit based on the criterion. Placement results from the CAD tool and the hardware placement unit are used to generate a placement solution for the system on the target device. Other embodiments are described and claimed.

Abstract: A method for optimizing a system on a target device is disclosed. A LUT is unpacked to form a plurality of LUTs of a smaller size upon determining that the unpacking can satisfy one or more predefined objectives. The plurality of LUTs are repacked such that the design for the system is improved. Other embodiments are disclosed.

Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract: A method for managing an agent includes verifying an integrity of the agent in response to a registration request. Memory protection is provided for the agent during integrity verification. An indication is generated when registration of the agent has been completed. According to one aspect of the present invention, providing memory protection includes having a virtual machine monitor limit access to the agent. Other embodiments are described and claimed.

Abstract: A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed.