Patents Represented by Attorney L. Cho

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  • Method and apparatus for communicating information from an operating system based environment of a server blade to the chassis management module
    Patent number: 7398401
    Abstract: A method for managing information from an operating system based environment includes determining whether the information is to be communicated to a chassis management module. The information is transmitted to a service processor upon determining that the information is to be communicated with the chassis management module.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: July 8, 2008
    Assignee: Intel Corporation
    Inventors: Gundrala D. Goud, Vincent J. Zimmer
  • Method and apparatus for measuring thread wait time
    Patent number: 7398518
    Abstract: A method for analyzing a program includes identifying code in the program having high thread wait time. A task associated with the code is identified as a potential source of performance problem for the program.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 8, 2008
    Assignee: Intel Corporation
    Inventor: Carl R. Dichter
  • Method and apparatus for measuring absolute and net power consumption for computer systems
    Patent number: 7383137
    Abstract: A method for managing power data includes determining an amount of power used for a system running an application over a first time period from an operating system. An amount of power used for the system in a baseline state over a second time period is determined from the operating system. A net power consumption of the application is determined from the amount of power used for the system running the application and the amount of power used for the system in the baseline state.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 3, 2008
    Assignee: Intel Corporation
    Inventor: Ulf R. Hanebutte
  • Method and apparatus for managing virtual addresses
    Patent number: 7383374
    Abstract: A method for managing virtual memory addresses includes associating a guest identifier (ID) with a virtual machine accessing a virtual memory address. A physical memory address is retrieved corresponding to the virtual memory address utilizing the guest ID. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 3, 2008
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Felix Leung, Amy Santoni, Asit Mallick, Rohit Seth, Gary Hammond
  • Method and apparatus for enabling waveform display in a system design model
    Patent number: 7360189
    Abstract: A method for generating a waveform display includes retrieving signal data associated with a node in a system design model from a system level electronic design automation tool. A value change dump file that describes the signal data is generated.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: April 15, 2008
    Assignee: Altera Corporation
    Inventor: Philippe Molson
  • Method and apparatus for performing retiming on field programmable gate arrays
    Patent number: 7360190
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: April 15, 2008
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Gabriel Quan, Terry Borer, Ian Chesal, Valavan Manohararajah, Karl Schabas, Stephen Brown
  • Method and apparatus for synchronizing data with a reduced clock cycle response time
    Patent number: 7360026
    Abstract: A data buffering unit includes a memory that stores data from a data transmitting device. The data buffering unit also includes a memory read manager that prepares data stored in the memory for output prior to receiving a request for the data from a data reading device.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: April 15, 2008
    Assignee: Altera Corporation
    Inventor: Neil Johnson
  • Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices to satisfy timing requirements
    Patent number: 7337101
    Abstract: A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: February 26, 2008
    Assignee: Altera Corporation
    Inventors: Steven Perry, Gregor Nixon, Ziad Abu-Lebdeh, Alasdair Scott, Philippe Marti
  • Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays
    Patent number: 7318210
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes placing new logic elements (LEs) at preferred locations on a layout of an existing system. Illegalities in placement of the new LEs are resolved.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: January 8, 2008
    Assignee: Altera Corporation
    Inventors: Deshanand P. Singh, Stephen D. Brown
  • Method and apparatus for three-dimensional tracking of infra-red beacons
    Patent number: 7310441
    Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: December 18, 2007
    Assignee: Intel Corporation
    Inventors: David J. Cowperthwaite, Bradford H. Needham
  • Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells
    Patent number: 7308671
    Abstract: A method for designing a system on a field programmable gate array (FPGA) includes performing mapping with a plurality of passes where a different assumption is made with respect to a property of the FPGA during each pass.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: December 11, 2007
    Assignee: Altera Corporation
    Inventors: Jinyong Yuan, Sinan Kaptanoglu
  • Apparatus and method for RTL modeling of a register
    Patent number: 7308659
    Abstract: The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: December 11, 2007
    Assignee: Altera Corporation
    Inventors: Gopinath Rangan, Guy Dupenloup, Wira Gunawan, Tzung-Chin Chang, Khai Nguyen
  • Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
    Patent number: 7308664
    Abstract: A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: December 11, 2007
    Assignee: Altera Corporation
    Inventors: Ryan Fung, Vaughn Betz, William Chow
  • Method and apparatus for reducing charge loss in a nonvolatile memory cell
    Patent number: 7291546
    Abstract: A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: November 6, 2007
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Fangyun Richter
  • Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
    Patent number: 7290239
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: October 30, 2007
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Valavan Manohararajah, Karl Schabas
  • Method and apparatus for implementing a multiple constraint length Viterbi decoder
    Patent number: 7260154
    Abstract: A Viterbi decoder capable of decoding a code having a maximum constraint length of Lmax is disclosed. The Viterbi decoder includes an initializer unit that initializes selected states of an encoder during an initial time period to allow the Viterbi decoder to also decode codes having a constraint length less than Lmax.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 21, 2007
    Assignee: Altera Corporation
    Inventors: Volker Mauer, Alejandro Diaz-Manero, Martin Langhammer
  • Method and apparatus for performing logic replication in field programmable gate arrays
    Patent number: 7257800
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: August 14, 2007
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Gabriel Quan, Terry Borer, Valavan Manohararajah, Paul McHardy, Ivan Hamer, Karl Schabas, Kevin Chan
  • Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
    Patent number: 7257795
    Abstract: Methods and apparatuses are disclosed to facilitate routing between a first and second component in a programmable logic device to generate a path with an appropriate amount of delay to satisfy short-path timing constraints efficiently and effectively.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 14, 2007
    Assignee: Altera Corporation
    Inventors: Ryan Fung, Michael Chan
  • Method and apparatus for optimizing delay paths through field programmable gate arrays
    Patent number: 7249339
    Abstract: A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: July 24, 2007
    Assignee: Altera Corporation
    Inventor: Bruce Pedersen
  • Method and apparatus for managing testing in a production flow
    Patent number: 7246283
    Abstract: A method for managing testing of test material is disclosed. An electronic traveler associated with the test material is identified. The test materials are tested as specified by the electronic traveler. Test results from the tests are recorded onto the electronic traveler.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: July 17, 2007
    Assignee: Altera Corporation
    Inventors: Naresh Mehta, Parmeshwar Reddy Bayappu, Kyle Bowers