Patents Represented by Attorney L. Cho

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  • Method and apparatus for implementing a processor interface block with an electronic design automation tool
    Patent number: 7895549
    Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: February 22, 2011
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Angled implantation for deep submicron device optimization
    Patent number: 7883946
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: February 8, 2011
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • Method and apparatus for deriving signal activities for power analysis and optimization
    Patent number: 7877710
    Abstract: A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: January 25, 2011
    Assignee: Altera Corporation
    Inventors: David Neto, Vaughn Betz, Meghal Varia, Gregg William Baeckler
  • Method and apparatus for implementing carry chains on field programmable gate array devices
    Patent number: 7873934
    Abstract: A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: January 18, 2011
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Method and apparatus for performing path-level skew optimization and analysis for a logic design
    Patent number: 7853911
    Abstract: A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: December 14, 2010
    Assignee: Altera Corporation
    Inventors: Ryan Fung, Vaughn Betz, David Karchmer
  • Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool
    Patent number: 7823092
    Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: October 26, 2010
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
    Patent number: 7818705
    Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 19, 2010
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, David Lewis
  • Method and apparatus for three-dimensional tracking of infra-red beacons
    Patent number: 7809161
    Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 5, 2010
    Assignee: Intel Corporation
    Inventors: David J. Cowperthwaite, Bradford H. Needhan
  • Method and apparatus for implementing a look-ahead for low radix Montgomery multiplication
    Patent number: 7801937
    Abstract: A method for performing Montgomery multiplication on n bit numbers includes computing look-ahead partial sum values to generate a Montgomery result after n/2+1 iterations of intermediate result computations. According to one embodiment of the present invention, Montgomery multiplication is performed to compute A*B mod M where A, B, and M are n-bit numbers.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: September 21, 2010
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Method and apparatus for scheduling virtual machine access to shared resources
    Patent number: 7797699
    Abstract: A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Alain Kagi, Andrew V. Anderson, Steven M. Bennett, Erik C. Cota-Robles, Gregory M. Jablonski
  • Method and apparatus for parameterizing hardware description language code in a system level design environment
    Patent number: 7793248
    Abstract: A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: September 7, 2010
    Assignee: Altera Corporation
    Inventor: David Van Brink
  • Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas
    Patent number: 7788614
    Abstract: A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. The one or more equations are modified, or supplemented by adding one or more additional equations, by applying spreading forces to the cells that take into consideration classification types of the cells and restricted areas on the target device that do not support the classification types. Revised locations on the target device are determined for the cells by solving the modified one or more equations.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: August 31, 2010
    Assignee: Altera Corporation
    Inventors: David Galloway, Ryan Fung
  • Method and apparatus for providing electrostatic discharge protection for a polysilicon fuse
    Patent number: 7782581
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a component on a device includes a grounding element coupled to a protected supply voltage line of the component. A supply pass element is coupled to the protected supply voltage line of the component. The ESD protection circuit also includes a control circuit to activate the grounding component to drive the protected supply voltage line of the component to ground upon detecting an ESD event.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: August 24, 2010
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Method and apparatus for reducing dynamic power in a system
    Patent number: 7774729
    Abstract: A method for designing a system on a target device includes inserting sequential elements into combinatorial logic bounded by a source sequential element and a destination sequential element to reduce glitching. The sequential elements are clocked with a clock signal having a phase difference from at least one of a clock signal clocking the source sequential element and the destination sequential element.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Altera Corporation
    Inventor: David Neto
  • Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
    Patent number: 7757197
    Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: July 13, 2010
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and apparatus for supporting immutable memory
    Patent number: 7739466
    Abstract: A method for managing a memory in a computer system is disclosed. A mapping of a virtual page to physical page is locked in response to receiving a request to make the page immutable. According to an aspect of an embodiment of the invention, locking the mapping of the virtual page to the physical page includes preventing mapping of the virtual page to another physical page. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Carlos Rozas, Mona Vij, David Bowler, Christopher Clark
  • Method and apparatus for performing parallel slack computation
    Patent number: 7725856
    Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 25, 2010
    Assignee: Altera Corporation
    Inventors: Jason Govig, David Karchmer
  • Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
    Patent number: 7712067
    Abstract: A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: May 4, 2010
    Assignee: Altera Corporation
    Inventors: Ryan Fung, Michael Chan
  • Method and apparatus for measuring temperature on a silicon device
    Patent number: 7708460
    Abstract: A method for measuring temperature on a silicon device includes activating a heat source on the silicon device. A value of a parameter of an electronic component on the silicon device is measured. A temperature associated with the electronic component is determined from the value of the parameter.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Altera Corporation
    Inventors: Jeffrey T. Watt, Shuxian Chen
  • Method and apparatus for managing software errors in a computer system
    Patent number: 7702966
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja