Abstract: A method for generating a linear block code is disclosed. A message is broken up into a plurality of sets of bits. A first group of sets is processed to determine a first partial linear block code. An adjusted partial linear block code is generated from the partial linear block code. A second group of sets is processed to determine a second partial linear block code. The adjusted partial linear block code and the second partial linear block code are combined into a single value.

Abstract: A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.

Abstract: A method for designing a system includes generating minimum and maximum delay budgets for connections from long-path and short-path timing constraints. The system is designed in response to the minimum and maximum delay budgets.

Abstract: A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first logic region are preserved. The first logic region is integrated with a second logic region having a second component in view of the determined properties.

Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Abstract: A method for performing feature tracking includes generating a pool of candidates on an image frame for a first feature point from information about a pool of candidates for a second feature point on a previous image frame.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.

Abstract: A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A location is determined for a user defined region on the target device that allows the system to satisfy timing constraints.

Abstract: A method for performing simulation on a circuit includes simulating registered and concurrent nodes in the circuit. Only concurrent nodes that are associated with a concurrent feedback loop are simulated until outputs of the concurrent nodes that are associated with the concurrent feedback loop reach a steady state.

Abstract: The Viterbi decoder includes a branch metric processor that determines branch metrics for states of an encoder in a time period. The Viterbi decoder includes a survivor processor that selects survivor paths between states of the encoder in consecutive time periods. The Viterbi decoder includes a normalization unit that normalizes state metrics of the states of the encoder in the time period by subtracting a constant.

Abstract: A system of permitting stack allocation in a program with open-world features is described. The system includes an escape analysis module to (1) determine which objects of the program can be stack-allocated under a closed-world assumption and (2) analyze, after stack allocation, which stack allocation is invalidated due to the occurrence of an open-world feature. A stack allocation module is provided to stack-allocate these objects based on the determination of the escape analysis module. A stack allocation recovery module is provided to recover those invalidated stack allocations back to their original allocation in heap based on the analysis of the escape analysis module. A method of permitting stack allocation in a program with open-world features is also described.

Abstract: A compiler includes a location-assigning module to optimally allocate register locations in various memory blocks of a memory during compilation of a program code in accordance with code proximity of the program code in accessing the register locations and size of each of the memory blocks.

Abstract: A programmable logic device (PLD) includes a plurality of programmable resources. The PLD includes configuration hardware that configures a first programmable resource at a first rate and a second programmable resource at a second rate with data that is provided to the configuration hardware at the first rate.

Abstract: A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.

Abstract: A method for managing a code sequence according to a first embodiment of the present invention is disclosed. Sets of n contiguous sample values that include sample values in a plurality of sample sequences are accessed. Sets of n contiguous coefficients are accessed. The sample values in each of the plurality of sets of sample values that are accessed are processed in parallel with corresponding coefficients that are accessed. Each of the plurality of sets of sample values are processed during a different time step.

Abstract: A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier.

Abstract: A squaring circuit for signed binary numbers includes a signed binary number modification unit that generates a modified signed binary number. The squaring circuit includes a partial product generation unit that generates partial products that make up a squared value of the modified signed binary number. The squaring circuit includes a correction value generation unit that generates a correction value for the signed binary number. The squaring circuit includes a summing unit that sums the partial products with the correction value to generate a squared value for the signed binary number.

Abstract: A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.

Abstract: A method for implementing a pseudo random sequence (PRS) generator is disclosed. Relationships between outputs of flip-flops of an initial model PRS generator at a current time step t with the outputs of the flip-flops at a time step t-n is determined, where n is a number of coefficients to be generated per time step. Flip-flops in the multi-step PRS generator are coupled in response to the relationships between the outputs of the flip-flops at the current time step t with the output of the flip-flops at the time step t-n.

Abstract: A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier.