Abstract: A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient "overdrive" for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level.

Abstract: A circuit is described for reducing the skew between a pair of signal lines in a digital system. Before the two lines display a change in signal the circuit senses whether the signals are similar or different. If similar, the two lines are clamped together in true fashion. If different, the two lines are clamped together complementarily such that the signals remain mutually inverted.

Abstract: A H-bridge circuit is disclosed using DMOST switches having current sensing parallel connected elements. An op-amp control circuit is coupled to the power and sense sources to force the sense source to the same potential as the power source. The op-amp circuit drives FET output devices which produce an output current proportional to the H-bridge current. A high voltage op-amp configuration is set forth.

Abstract: A voltage is provided by a master circuit and received by a plurality of slave circuits over a bus. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit coupled to the bus. Each of the slave circuits has a pair of transistors coupled to the bus in an emitter-follower configuration to step down the voltage from the master circuit and to provide a voltage reference. The voltage provided to the bus varies as it propagates through the bus. Accordingly, a plurality of unconnected resistors are formed in the portions of the silicon substrate which contain the master and/or slave circuits. When formed in the master circuit, the resistors are located in the V.sub.bb reference circuit. When formed in the slave circuit, the resistors are located in close proximity to the output transistors.

Abstract: An ECL cutoff driver circuit for an ECL gate coupled between ECL high and low potential power rails includes a cutoff clamp circuit. The ECL gate with differential signal inputs and at least one output node is coupled for delivering ECL logic output signals of high and low potential levels during operation of the ECL gate in a switching mode. The cutoff driver circuit includes cutoff transistor elements for shifting down the ECL output at least to a maximum specified cutoff potential level below the ECL logic low potential level in a cutoff state. The cutoff clamp circuit is coupled between the ECL high potential power rail and the output node or output nodes for clamping the ECL output at a minimum or lower bound voltage level substantially at the specified cutoff voltage level V.sub.OLZ. This prevents output buffer transistor elements from being completely turned off for faster return of the ECL gate from the cutoff state to operation in the switching mode.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.

Abstract: A DMOST driver circuit responds to the current flowing in the DMOST and the voltage appearing across it. The current and voltage are multiplied together in a g.sub.m amplifier which is coupled to drive a first input of a diff-amp. The diff-amp has its second input coupled to a source of reference potential. The diff-amp output is coupled to the DMOST gate to create a stabilizing negative feedback loop. The first diff-amp input is also coupled to a reference potential related threshold voltage so that the drive to the DMOST will be controlled by the DMOST power dissipation multiplied by a predetermined constant which is chosen to provide a safe dissipation level.

Abstract: A novel method and structure is taught for synchronizing a received digital data stream to the receiver clock. A plurality of delay lines; are used to provide a plurality of delayed input signals, which are then compared with the receiver clock signal in order to determine which of the delayed input signals is closest in phase to the receiver clock signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed input signals for use by the receiver. In an alternative embodiment, a plurality of delay lines are used to provide a plurality of delayed clock signals, which are then compared with the receiver input signal in order to determine which of the delayed clock signals is closest in phase to the receiver input signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed clock signals for use by the receiver.

Abstract: The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit provides the OE signals of high and low potential to the OE cutoff driver gate. The OE cutoff driver current sink for sinking current from the OE cutoff driver gate is provided by a current switch circuit for switching sinking current on and off in response to current switch signals of high and low potential in phase with the OE signals. The current switch circuit switches on sinking current when the OE cutoff driver gate is holding the ECL logic gate in the cutoff state. The current switch circuit switches off sinking current for reducing power dissipation when the ECL logic gate is out of the cutoff state. The current switch circuit is provided by a current mirror circuit.

Abstract: A combined CMOS/linear circuit employs a voltage reference circuit to provide a temperature compensated V.sub.REF output. The circuit includes means for switching the reference circuit off and on in response to the signal on an enable terminal. The voltage reference circuit includes a current mirror feedback which is positive in nature to provide a controlled hysteresis action. This provides noise immunity for the enable input. A digital output indicator is included to indicate the state of the reference circuit.

Abstract: A translator-translator logic (TTL) to emitter coupled logic or current mode logic (ECL/CML) input buffer and translator circuit provides temperature compensated input and threshold signal voltage levels to a translator circuit ECL gate for improved operation of the translator circuit. A threshold clamp circuit is coupled between an on-chip band-gap bias generator and the base node of the reference transistor element of the translator circuit ECL gate. The threshold clamp circuit maintains a substantially fixed temperature compensated reference voltage or threshold voltage level at the base node of the reference transistor element, referenced to the temperature compensated current source voltage level V.sub.cs from the bias generator. An input clamp circuit also references the logic high signal voltage level V.sub.TH at the base node of the ECL gate input transistor element to V.sub.CS.

Abstract: An improved tape automated bonding method of bonding the beam leads of lead frame tape to gold bumps formed on the contact pads of a semiconductor device, wherein the tape includes a plurality of interconnected beam leads defined by at least one opening in the tape such that each beam lead has an inner end and an outer end. The method includes the steps of depositing a gold layer on the beam leads, masking a region of each beam lead from further deposition of material such that a predetermined portion of each beam lead is exposed for further deposition of material, depositing a predetermined amount of tin on the exposed portion of each beam lead, establishing contact between each beam lead and the die bump to which each beam lead is to be bonded and applying a predetermined amount of pressure and heat to form a bond between each beam lead and the die bump to which the beam lead is to be bonded such that the bond formed includes the primary eutectic of the combination of tin and gold.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

Abstract: An improved process is described for the formation of PNP transistor collector base junctions or PN junction capaciters in silicon monolithic integrated circuits that employ the ion implantation and diffusion of aluminum in these regions that are to contain high performance PNP transistors or capacitors. The process reduces or eliminates the leakage typically found in such devices.

Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Abstract: An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation threshold operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate for shifting the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate.

Abstract: An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region.