Abstract: A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.

Abstract: A process is disclosed for forming high-performance high-voltage PNP transistors in a conventional monolithic, planar, PN junction isolated integrated circuit that contains high-performance NPN transistors. The process permits independently optimizing the NPN and PNP transistors.

Abstract: A process is disclosed for forming a planarized or smooth surface binary glass insulating film comprised of germanium dioxide and silicon dioxide by a spin-on process. The resulting structure has a film thickness uniformity which varies less than 5% over the surface of the wafer. The structure is formed by mixing a predetermined solution of TEOS and TEOG in a lower alcohol or ketone solvent and catalyzing by the addition of sufficient acid to raise the pH to 1.5 to 2.0 to favor gel formation. The resultant solution is then spun on at an RPM selected to give the desired film thickness for a given solids content of the solution.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A circuit for providing a voltage reference level using a master circuit and a plurality of slave circuits. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit. Each of the slave circuits has a pair of transistors in an emitter-follower configuration to step down the voltage and drive the circuitry requiring the voltage reference.

Abstract: A process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is disclosed. The process begins with a structure having a P type substrate 10, an N type epitaxial layer 15, and an intervening N type buried layer 12. The process includes the steps of removing all of the epitaxial layer 15 and all of the buried layer 12 from regions of the substrate where NMOS devices are to be formed, to thereby leave second regions of the epitaxial layer 15 and buried layer 12 having sidewalls 21 protruding above the substrate 10. A layer of silicon dioxide 25 is formed at least over the sidewalls of the protruding regions, and then a further epitaxial deposition of silicon is employed to reform the epitaxial layer 28 over the first regions, which epitaxial layer 28 is separated from the previously formed epitaxial layer 15 by the silicon dioxide isolation 25. The process continues by fabricating bipolar and field effect transistors in separate ones of the first and second regions.

Abstract: A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.

Abstract: A voltage regulator circuit is set forth in which the series pass transistor has its high impedance (collector/drain) electrode connected to the output terminal and a shunt transistor has its low impedance (emitter/source) electrode connected to the output terminal. The circuit is arranged to ensure that the shunt transistor is always conductive so that its low impedance electrode will stabilize the operation of the circuit without requiring any external components. The circuit can be fabricated in either bipolar or CMOS form and a low dropout configuration is employed.

Abstract: A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.

Abstract: A circuit is shown in which a voltage regulator has an output stage that operates as a Darlington when the input-output differential exceeds a threshold. The circuit automatically switches to a common emitter output and an emitter-follower driver when the differential falls below the threshold. A current limiter prevents excessive common current when the output transistor is saturated.

Abstract: A Darlington output stage is shown in which the saturation voltage is reduced to the level of a single common emitter output transistor. The circuit includes a lateral feed-forward transistor that bridges the driver transistor. A resistor is included to ensure that the driver transistor is turned off when the output transistor saturates. An IC version of the circuit is set forth in detail.

Abstract: In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of alumimum, nickel-vanadium alloy and gold. The bumps are then created by electroplating gold through openings in a photoresist mask. The gold bumps are overcoated with a controlled thickness tin layer and the tin is overcoated with a thin gold anticorrosion layer. The copper assembly tape is coated with a thin gold layer and are lightly pressed against the bumps by means of a thermode. The thermode is quickly heated to a temperature well above the gold-tin eutectic melting temperature and then rapidly cooled. The tin layer on the bump will combine with the adjacent gold to form a liquid phase eutetic which will form and contact both the copper finger and the gold bump. Upon cooling the eutectic melt will solder the finger to the bump.

Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

Abstract: A novel multistep flash analog to digital converter is taught, including a voltage estimator which quickly provides a rough estimate of the analog input signal. This rough estimate is used to select appropriate reference voltage tap points for use in the first flash conversion. This first flash conversion, together with the voltage estimate, provides the most significant bits of the digital output word. A digital to analog converter is used to provide a residual voltage which is then converted by a second operation of the flash converter, thereby providing the least significant bits of the digital output word. In one embodiment, the voltage estimate is performed at the same time that the analog input signal is sampled by the flash converter in preparation for the first flash conversion. Therefore, speed of operation is not degraded by the addition of the voltage estimator.

Abstract: A CERDIP housing is provided with a heat pipe that passes through the closure seal lid whereby the heat pipe terminates within the housing cavity at the hot end thereof. A quantity of working fluid, such as fluorinated octane, is contained within the package cavity. The heat pipe communicates with cooling fins that produce a cold end thereof. Heat from the semiconductor device inside the housing boils the working fluid and is cooled thereby. The fluid vapor passes along the heat pipe and is condensed at the cold end to be converted back to liquid. As a result the semiconductor device is in direct communication with the heat pipe working fluid.

Abstract: A process is disclosed for forming high-performance, high voltage PNP and NPN power transistors in a conventional monolithic, planar, epitaxial PNP junction isolated integrated circuit. The process permits independently optimizing the NPN and PNP power trransitors. Where high-voltage devices are desired a field threshold adjustment implant is applied. It also includes provisions for testing critical portions of the process at appropriate points.

Abstract: A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.

Abstract: A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.

Abstract: A low dropout voltage regulator with quiescent current reduction has a pass transistor coupled for conduction from a positive supply terminal to a regulated output terminal. A first switch is coupled to conduct the base current of the pass transistor to the regulated output terminal. A second switch is coupled to conduct the base current of the pass transistor to ground. A control circuit selects the action of the switches to select the conduction path for base current.

Abstract: An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.