Abstract: A CMOS relaxation oscillator is disclosed employing a pair of capacitors and individual charging means. A noninverting amplifier comprising two cascaded inverters is provided with a transmission gate input circuit that alternately switches the amplifier input between the two capacitors. A pair of switches coupled respectively across the capacitors alternately discharge them. The resulting oscillator has a frequency determined by the capacitor charging periods. Accordingly, the frequency and duty cycle can be predetermined as desired. The circuit can also be made either power supply tunable or power supply independent.

Abstract: An improved Schottky barrier diode for increasing the alpha particle resistance of static random access memories includes an extra implanted N-type region at the surface of the epitaxial layer to increase the impurity concentration there to about 1.times.10.sup.19 atoms per cubic centimeter. In one device, arsenic is employed to overcompensate a guard ring where the Schottky diode is to be formed, while in another device phosphorus is employed and the guard ring is not overcompensated. The resulting Schottky diodes, when employed in the static random access memory cells, dramatically increase the alpha particle resistance of such cells, while also substantially decreasing the access time.

Abstract: An integrated circuit assembly (10) includes a bipolar VLSI die (12) contained in a multilayer ceramic pin-grid array package (14). A bonding shelf (18) defined on a single ceramic layer contains an inner row (20) of bonding pads (26) and an outer row (22) of bonding pads (28). Bonding wires (30, 32) extend from bonding pads (34) on the die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the package. The inner and outer bonding pads are connected by metallized fingers to conductive pads (61, 65) which provide a power and signal interface with an incorporating system.The inner pads include metallized vias (24) to metallized segments on a layer other than that on which the bonding shelf is defined. Thus, the metallized fingers including the inner row of pads can extend to the pins while passing above or below, rather than between, adjacent pads of the outer row.

Abstract: A CMOS structure is employed to create an isolated large area power output transistor along with a voltage multiplier that acts to develop an overdrive bias in response to clock pulses. The circuit can be employed to couple a relatively low power supply voltage to an output terminal while encountering a small voltage drop across the power transistor.

Abstract: A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors and a pair of current sources. A differential amplifier is coupled to operate in parallel with the mutlivibrator and its tail current is operated differentially, with respect to the currents in the pair of sources, in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscillator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithmic response for digital signaling processing.

Abstract: A silicide base shunt 50 and method of fabricating it are disclosed for a bipolar transistor. The base shunt 50 is fabricated using the first layer metal 36, 39 as a mask to etch silicon dioxide 27 surrounding the emitter 34 to thereby expose the underlying silicon epitaxial layer 24. Nickel or copper are then deposited onto the silicon 24 to form a region of silicide 50 extending from a base contact 36 to closely proximate the emitter 34, thereby minimizing the resistance of the extrinsic base region 24 of the transistor.

Abstract: A new permutation bit map architecture is described for flexible cellular addressing, image creation, and frame buffer control in raster graphics machines. A new frame buffer address generator and address circuitry accesses frame buffer memory locations with different word and cell configuration addressing modes to increase performance and efficiency. A new graphics image data generator creates, modifies, and updates graphics image data in the frame buffer memory locations accessed by the multiple addressing mode word and cell configurations of the address generator and address circuitry. The graphics image data generator provides vector drawing, polygon filling, "Bit Blt's" or bit block transfers, alignment and masking of graphics image data, and refresh display of a raster view surface. Vector drawing is achieved with greatly increased performance because of the multiple cellular addressing modes of the addressing circuitry.

Abstract: An input protection structure effectively protects input circuitry from positive-going ESD pulses. The input protection structure includes a transistor having a reduced beta, connected in series with one or more diodes between the input pin and VCC. In one embodiment, the transistor having reduced beta is constructed in the same manner as a fuse device. The structure is formed in an integrated fashion, without the need for metallic interconnections within the structure itself, thereby decreasing impedance while minimizing surface area in the integrated surface.

Abstract: A molded pin-grid-array package includes a heat sink available at the face opposite to the pins. The heat sink is secured to a printed wiring board that has plated through holes therein that form the desired pin-grip-array and wires are secured in the holes to form the package pins. The heat sink covers an aperture in the board and the semiconductor die is secured to the heat sink inside the cavity thereby formed. After the semiconductor die is attached and the bonding pads connected to the metal traces on the board, the assembly is placed in a transfer mold. Plastic encapsulant is then transfer molded to encapsulate the semiconductor die and to extend flush with the heat sink to form a skirt around the periphery of the board. This leaves the molded package with an available heat sink face for efficient cooling after the package is mounted for ultimate use.

Abstract: A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.

Abstract: In accordance with the teachings of this invention, a novel PLA row driver circuit is provided which utilizes a minimum number of components, thereby minimizing integrated circuit surface area, and thus reducing cost, and minimizing stray capacitance, thereby increasing speed of operation. Furthermore, in accordance with the teachings of this invention, a circuit is provided which, while utilizing a minimum number of components, provides a first VOL level to the row line during normal operation of the device, and a second, higher VOL level to the row line during programming.

Abstract: A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.

Abstract: A temperature compensated ECL gate (20) with each gate circuit resistance formed by a pair of opposite polarity temperature coefficient resistors. A first gate transistor element (Q1) and a second gate transistor element (Q2) coupled at a common emitter coupling (12) provide alternative collector current paths from high potential (V.sub.cc) through a first gate transistor collector path with collector resistance (R11,R12) and a gate transistor collector path with collector resistance (R21,R22). A current source transistor element (Q3) is coupled between the common emitter coupling (12) of the gate transistor elements and low potential (V.sub.EE) through current source resistance (R31,R32). The resistances of the ECL gate each include a positive temperature coefficient silicon first resistor (R11,R21,R31) and a negative temperature coefficient low capacitance polysilicon second resistor coupled (R12,R22,R32) in series.

Abstract: An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer (32), over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide (34). Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.

Abstract: An improved integrated circuit die with multiple circuits on the same substrate of semiconductor material is formed with circuit elements of the multiple circuits grouped respectively into at least first and second circuit areas or sections of the die. The first and second circuit sections of the die are separated and spaced from each other by a moat or separating boundary line. The separating boundary line is formed using appropriate mask lines on the fabrication masks. The separating boundary line is composed of the substrate semiconductor material between the circuit sections. The separating boundary line is formed without implanting buried collector layers or channel stop regions in the substrate semiconductor material of the boundary line width and depth. Relatively high resistive substrate isolation of the circuit sections of the die reduces feed through coupling of AC signal between circuit elements of the respective circuit sections.

Abstract: A switching voltage regulator is stabilized against changes in input voltage by suppressing the increase in loop gain due to increased input voltage. The reduction of loop gain is achieved by use of a modified triangle waveform which is compared to an error signal to switch the regulator output stage.

Abstract: According to the teachings of this invention, a novel sense amplifier is provided which includes a current steering transistor having its emitter connected to the collector of a current mirror transistor, its collector connected to the base of an output transistor, and its base driven by the input signal. With a low input signal, the emitter of the current steering transistor is pulled low, thereby pulling the base of the output transistor low. Conversely, when the input signal is high, and the current steering transistor ceases to operate in the active saturation mode and begins to operate in the inverse active saturation mode, thereby providing current from its base to its collector in order to turn on the output transistor.

Abstract: An expandable ECL matrix shifter is provided to have very few interconnecting wires. The shifter can perform a multicolumn right shift or a multicolumn left shift in one cycle, and it has independent wrap and fill capabilities. Two 2 to 1 multiplexers are provided for each bit position of the input signals. The input signals provide one of the inputs for both of the multiplexers. The second input of each multiplexer is a signal indicating what type of fill is desired. The shifter has horizontal data input lines, vertical data output lines, and diagonal select lines. A bipolar transistor is located at each intersection of a data input line and a data output line. These transistors selectively connect the data input lines to the data output lines in response to signals on the diagonal select lines. Each horizontal data input line is divided into two parts. The division of the data input lines into parts is along a major diagonal of the matrix.

Abstract: An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. the indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved.

Abstract: Spot defects are detected utilizing an apparatus which comprises a meander structure formed in a high resistivity material on a substrate. The meandor includes intermediate segments, the ends of which are interconnected by folded segments such that an electrical circuit having electrical resistance R is formed between the ends of the meander. A strip of high electrical conductivity material is formed in substantial alignment with and is electrically insulated from a corresponding one of each of the intermediate segments. Each end of each strip is electrically connected to a corresponding end of a corresponding intermediate segment. Defects are identified by measuring the resistance R, between the ends of the meander. This measured value is then compared to the calculated value of R. If the value of the measured resistance is substantially smaller than the calculated value, a flaw due to a spot of additional high conductivity material, is considered to be present.