Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be inspected by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.

Abstract: A programmable logic array having a number of inputs for receiving operand data and a number of outputs for furnishing the results of Boolean operations upon the operand data is provided with a precharge signal generator responsive to a state transition in the operand data for generating a precharge signal. The buffered operand data is furnished to an AND plane, and pullup circuits associated therewith are responsive to the precharge signal for charging the AND plane and sustaining the charge on all AND plane array lines in the logical ONE state. An OR plane is connected to the outputs of the AND plane, and pullup transistors associated with the OR plane and responsive to the precharge signal for charging the OR plane and sustaining the charge on all OR plane array lines in the logical ONE state. The PLA outputs are taken from the buffered outputs of the OR plane.

Abstract: A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: A circuit and structure intended for use in CMOS IC designs acts to protect signal lines against ESD. An array of three transistors is connected so that the voltage pulse that appears on the signal line as a result of ESD, forces at least one transistor into conduction. The circuit responds equally to positive and negative pulses and is, therefore, symmetrical, and independent of bias or supply potentials. In the absence of an ESD pulse the circuit draws a very low leakage current and, therefore, has very little effect upon normal IC operation.

Abstract: A method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, an intermediate etch stop barrier layer, and a second metallization sublayer. Usually, a barrier layer will be formed between the substrate and the laminated metal structure. The laminated metal structure is then patterned into the desired vertical metal interconnects, which interconnects are at different elevations because of the uneven underlying surface. The vertical metal interconnects are then planarized by first applying a dielectric layer and a sacrificial layer, etching back the combined dielectric and sacrificial layers to expose only the higher vertical metal interconnects, and then selectively etching back the second metal sublayer component of the higher vertical metal interconnects.

Abstract: A BiCMOS voltage reference generator circuit generates and maintains a reference voltage within 3 mV over an 80.degree. C. temperture range and over a 1 volt change in power supply level. The circuit uses feedback from the output of the reference voltage generator to the current source supplying current to the voltage reference generator. This feedback increases the effective output impedance of the current source, making the reference voltage output substantially independent of power supply variations. The circuit operates with power supply differential as low as about 3 volts, and preferably is fabricated from bipolar transistors and MOS transistors on the same chip.

Abstract: A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.

Abstract: An improved copper bump tape for tape automated bonding inhibits electromigration of the copper after bonding to a semiconductor device. The improved tape is characterized by the plating of a migration resistant metal onto the inner ends of connector beams of the tape. The migration resistant metal is coated onto all surfaces of the connector bump, except for the surface which is to be bonded to the semiconductor device. In this way, the surfaces of the bump which remain exposed after connection to the semiconductor are inhibited from electromigration.

Abstract: A soft start circuit for a switching regulator is disclosed. The circuit does not require any off-chip parts and, therefore, a five-pin package can be employed. The operation of a soft start circuit in conjunction with a switching regulator operating in the voltage boost mode is set forth in detail.

Abstract: A liquid polymeric resin is applied over an irregular surface of a semiconductor substrate by first spinning followed by rotation of the substrate about an axis parallel to and spaced-apart from the plane of the substrate. Such a technique provides for planarization layer having enhanced planarity. When applied over an underlying insulating layer, the planarization layer will typically be etched back in order to planarize the insulating layer. Alternatively, the planarization layer may be formed directly over the semiconductor substrate, and an insulating layer formed over the planarization layer. In either case, the substrates are then ready for subsequent processing according to well known techniques, typically the formation of metallization layers over the insulating layer.

Abstract: A switched capacitor amplifier circuit using a pair of switched capacitors to replace each resistor element of an inverting operational amplifier circuit, with the capacitors operating on opposite halves of the switching cycle to provide reduced sampling distortion.

Abstract: A bonding apparatus for eutectically bonding tape leads to semiconductors and other substrates includes four separate bonding rails for applying heat. The bonding rails have a preselected distribution of mass along their length in order to compensate for uneven heating characteristics which are normally observed in linear heating elements. Usually, four such heat elements are orthogonally arranged at the bottom ends of four electric power buses. By attaching the heating elements to adjacent power buses, and coupling diagonally opposed pairs of the power buses to the positive and negative polarity of a current source, substantially uniform heating of all four elements may be achieved. The ability to provide uniform heating is critical for properly forming eutectic bonds.

Abstract: In a monolithic silicon integrated circuit fast diffusing impurities are incorporated into the collectors of the bipolar lateral transistors. The impurity level is controlled, using ion implantation, so that after device processing the lateral transistor collectors extend an additional increment into the base. This increment is doped with the fast diffusing impurity at a level that overcompensates the normal base impurity to the opposite conductivity type and conductivity about equal to that of the base. Thus the collector junction is moved towards the emitter and is symmetrical in terms of conductivity. This means that when the collector is reverse biased the depletion field extends about equally on both sides of the junction. This action greatly relieves the voltage gradient and stress so that collector junction voltage breakdown is enhanced. Since the collector junction is closer to the emitter the transistor current gain and frequency response are enhanced.

Abstract: A pair of voltage triplers are formed in a C/DMOS circuit along with a self-isolated DMOS transistor. The voltage triplers are driven in phase opposition from the system clock and their outputs commonly drive the gate of the DMOS transistor which acts as the pass element in a voltage regulator. A control circuit includes a reference voltage generator and a differential amplifier that senses a fraction of the d-c output voltage. The amplifier has an output coupled to the DMOS gate thereby to create a stabilizing negative feedback loop. The voltage triplers overdrive the DMOS transistor so the dropout voltage is low and the full wave rectifier action will double the clock frequency for easier filtering.

Abstract: An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out portions (15) extending to probe ends (19). Interconnect cross-links (16) initially connect the finger contacts and the tape edges and function as dam bars in subsequent encapsulation steps. The die and die bonds are mold encapsulated to form the die package (20) and a carrier frame (17) is simultaneously molded around and spaced from the periphery of package (20). The probe ends are exposed within a slot (34) in the frame or extend from the ends of the frame so that probe tips can be pressed thereon to test the die and its bonds. Prior to testing, the interconnects exposed in the annulus between the package and the carrier are blanked out so that each finger leading from a die contact pad becomes discrete, i.e.

Abstract: The copper tape that is used in the tape assembly of semiconductor devices is provided with a bondable surface by an electroplated layer of copper. The copper tape is passivated in a weak organic acid solution immediately after plating. In the preferred embodiment the copper tape is also cleaned and passivated prior to electroplating. The passivated copper can be thermosonically bonded using gold wires for up to 144 hours after preparation. The elimination of noble metal plating reduces assembly cost and the passivated copper bonds well to the subsequently applied plastic encapsulant.

Abstract: A feed mechanism for a tape applying machine in the semiconductor lead frame arts, especially suitable for discrete pieces of lead frame, in which pins are inserted into holes in the lead frame and advanced periodically. The pins are deliberately made smaller than the holes and moved in such a way as to always return to the center of the holes, well clear of the edges, before entering or withdrawing from the holes.

Abstract: A shipping tray that can be adjusted to various internal dimensions, by different placement of one or more moveable partitions. The partitions are held in position by means of interlocking surfaces formed on the ends and bottom of the partition and on the inside walls and interior bottom of the tray.

Abstract: A unique circuit that unambiguously provides an output status bit and an output delta bit in response to an input data signal. This circuit does not require the use of a one shot. The circuit includes a first latch which latches the last status value, and an exclusive OR gate for comparing the previous input data value with the present input data value and provides an output data signal indicating whether change in the input data has occurred. If the exclusive OR gate indicates that a change in input data has occurred since the previous read, the new value of the input data is provided as an output status signal. Conversely, if the exclusive OR gate indicates that a change in the input signal has not occurred, the previous value of the input signal stored by the circuit is provided as an output status signal. Additional latches, which close at the onset of a read cycle, prevent either the delta bit or the status bit from changing during the read cycle.