Abstract: A differential input stage for an operational amplifier includes a transistor pair differentially connected and supplied with tail current through a series resistor. The tail current is supplied by a pair of current amplifiers having their outputs coupled to the tail current resistor. The current amplifier inputs are coupled to the bases of the input transistor pair so that they are differentially driven. If the tail current resistor is properly selected the differential output current is a linear function of the differential input voltage. A clamp is provided for the differential input at some relatively large input signal voltage.

Abstract: A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A high speed buffer circuit is composed of complementary symmetry emitter follower driver and output stages. The input of driver stage includes active load devices cross-coupled to the output stage inputs so that the output stage is bootstrap driven from emitter followers. The circuit is biased by level shifting means to operate as a class AB current amplifier. It displays a wide bandwidth along with a high slew rate and can source or sink a large pulsed current.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.

Abstract: A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins.

Abstract: A wide bandwidth amplifier is coupled to the differential output of a four-quadrant multiplier. The amplifier includes a differential to single-ended input stage driving the inverting input of an operational amplifier which has its noninverting input operating at a reference potential level. The amplifier output is coupled by way of a level shifting means to the circuit output terminal which is thereby referenced to ground potential. The circuit output terminal is returned through a resistor to a source of opposite polarity power supply so that the output terminal can swing above and below ground. The second supply is only connected by way of the output terminal so that it does not require an extra package pin.

Abstract: A process for bonding silicon die to a package. This process comprises the following steps: (a) providing to the back surface of the die an adhesion layer of material which exhibits superior adhesion to both the silicon die and a subsequently applied barrier layer; (b) providing to the adhesion layer a barrier layer which is impervious to silicon; (c) providing to the barrier layer a bonding layer; and (d) bonding the die to the package by activating a binder composition disposed at the interface of the package and the bonding layer. The barrier layer prevents the migration of silicon to the bonding layer, both at the time of application of the bonding layer to the die and at the time of bonding the die to the package. The adhesion layer enhances the adhesion of the barrier layer material to the back surface of the die. Titanium is the preferred adhesion layer material while tungsten is the preferred barrier layer material.

Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be insepcted by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.

Abstract: There is disclosed a high performance MOS transistor structure of either the N channel or P channel variety and a high performance bipolar transistor structure. A process is disclosed which can make high performance CMOS and high performance bipolar devices on the same die.

Abstract: A silicon nitride layer is prepared on the surface of a silicon substrate by carrying out a surface reaction on the substrate in a vacuum chamber that contains an electrode which is capacitively coupled to an rf generator. A second electrode within the chamber, or a metal wall of the chamber itself, is connected to ground. The silicon substrates to be treated are placed on one of the electrodes to be in electrical and physical contact therewith, and a reagent gas that contains nitrogen is introduced into the chamber. An rf voltage is then applied between the electrodes to ionize and activate the gas, and cause ions and other active species thereof to be directed into the silicon substrate. The nitrogen ions and other active species that are created as a result of the application of the rf power can be directed at the surface of a number of wafers simultaneously.

Abstract: A method of fabricating polycrystalline silicon resistors having nearly zero or positive temperature coefficient includes the steps of depositing a layer of polycrystalline silicon, implanting the layer with silicon to make the layer substantially amorphous, introducing an impurity to dope the layer, and annealing the layer.

Abstract: A deglitching network for digital logic circuits includes a voltage actuated current source coupled to a linear tracking, constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predetermined voltage of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and its voltage falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A peaking capacitor for use with a differential input stage in an integrated circuit. The stage includes emitter degeneration resistors and a peaking capacitor coupled between the emitters. The capacitor is formed of MOS capacitors located over thinned oxide portions that lie within the confines of doped regions forming PN junctions with the semiconductor substrate. The doped regions are spaced apart by a distance that will result in depletion region reach-through at a voltage that is lower than the thinned oxide breakdown voltage. Thus, the structure is self-protecting and therefore resistant to electrostatic discharge damage. The capacitor that is formed has a value that is determined accurately by the area of the thinned oxide. It also has a low stray capacitance which makes it useful as a peaking capacitor.

Abstract: A CMOS current sense amplifier is composed of an output inverter gate, a combined driver and biasing stage that biases the output inverter gate and drives its transistors, and an input stage that acts to reduce the input voltage swing. The circuit responds rapidly to input current changes and is therefore useful in sensing the currents in large memory arrays that have large shunt capacitance values.

Abstract: Two insulating layers may be employed to define boundaries of junctions in transistor structures useful in integrated circuit fabrication. The junctions may overlie one another, have approximately equal areas, and terminate in the insulating layers.

Abstract: A lead frame that is suited for use on array types of integrated circuit packages to provide a high degree of compliance for absorbing mechanical stress induced by thermal changes includes a series of individual terminal elements that are connected in a strip form by means of break tabs disposed between adjacent elements. Each terminal element provides two spaced, generally parallel mounting surfaces that are resiliently connected to one another by means of an integral intermediate section. While the terminal elements are interconnected in strip form, one of the mounting surfaces of each element can be bonded to an associated attachment region on the semiconductor substrate. After all of the terminals of the strip have been so bonded, the break tabs between adjacent terminals can be removed to thereby separate the terminals from one another. The package which then results contains discrete compliant terminals which are suitable for subsequent surface attachment to the printed circuit board.

Abstract: A bipolar/CMOS process includes bipolar transistors having emitters formed in less than a minimal masking dimension. An opening is formed through a polycrystalline silicon layer deposited on a silicon substrate. After coating the sides of the opening with silicon dioxide, the intrinsic base region of the bipolar transistor and the emitter region are implanted. The extrinsic base is formed by outdiffusion from the polycrystalline silicon layer. The structure includes an epitaxial layer which is more strongly doped below its surface than at its surface to enhance the performance of CMOS transistors formed therein. Additionally, the bipolar and complementary MOS transistors are self-aligned to each other by the manner in which the buried layers are formed.