Patents Represented by Attorney Leffert Jay & Polglaze, P.A.

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  • NAND step voltage switching method
    Patent number: 8111555
    Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: February 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Taehoon Kim, Doyle Rivers, Roger Porter
  • M+N bit programming and M+L bit read for M bit memory cells
    Patent number: 8111550
    Abstract: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 7, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
    Patent number: 8107296
    Abstract: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Configuration finalization on first valid NAND command
    Patent number: 8103805
    Abstract: A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current consumption, and normal operation begins without the need for using an unreliable low voltage power on reset circuit.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Programming error correction code into a solid state memory device with varying bits per cell
    Patent number: 8103940
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Programming a memory with varying bits per cell
    Patent number: 8102706
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Transistor having peripheral channel
    Patent number: 8102709
    Abstract: Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Mikhalev
  • Systems and methods for erasing a memory
    Patent number: 8098530
    Abstract: Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing cells have their erasing throttled using a positive bias on their access line once a particular number of cells coupled to the access line are erased to the intermediate erase voltage.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sarin
  • Memory block testing
    Patent number: 8094508
    Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
  • Macro and command execution from memory array
    Patent number: 8095834
    Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Benjamin Louie
  • Memory erase methods and devices
    Patent number: 8089816
    Abstract: Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Tomoharu Tanaka
  • Memory media characterization for development of signal processors
    Patent number: 8090999
    Abstract: Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs. Models are developed from capturing output of memory devices of the type utilizing analog signals to communicate data values of two or more bits of information. The models are used to generate signals representative of the expected output of a memory device having an input data pattern. Read channels and/or controllers then process those signals to determine an output data pattern. By comparing the output data pattern to the input data pattern, the accuracy of the signal processing can be gauged.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Direct secondary device interface by a host
    Patent number: 8090886
    Abstract: A device has a controller and a function module configured to be in communication with the controller as a result of the controller receiving a pass-through vendor specific command. In some embodiments the controller may configured to strip data intended for the function module from the vendor specific command and send the stripped data to the function module.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Anson Ba Phan, Jerrold Allen Beckmann
  • Two-part programming methods and memories
    Patent number: 8089805
    Abstract: Programming a memory in two parts to reduce cell disturb includes, in at least one embodiment, programming data in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Allahyar Vahidimowlavi
  • N well implants to separate blocks in a flash memory device
    Patent number: 8084843
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Non-volatile memory device having assignable network identification
    Patent number: 8086790
    Abstract: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Charge loss compensation during programming of a memory device
    Patent number: 8085591
    Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Daniel Elmhurst, Giovanni Santin
  • Memory device with user configurable density/performance
    Patent number: 8082382
    Abstract: The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: December 20, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Memory device initiate and terminate boot commands
    Patent number: 8082435
    Abstract: Memory devices and methods facilitate initiation and termination of boot data output from a memory device through the use of received commands. For example, boot data output is initiated in response to a command indicative of a desire to enter a boot mode of operation. The initiate boot command may include a base command and a unique argument indicative of a desire to enter the boot mode of operation. Boot data output may be terminated by a received command indicative of a desire to terminate the boot mode of operation. The terminate boot command may include the same base command as the initiate boot command with any argument other than the argument indicative of a desire to enter the boot mode of operation.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: December 20, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Uche Ugokwe
  • Programming a memory device to increase data reliability
    Patent number: 8077519
    Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar