Abstract: A diffusionless source/drain conductor, electrically-erasable, electrically-programmable read-only memory cell is formed at a face of a semiconductor layer (38) of a first conductivity type and includes a source conductor (10), a drain conductor (12), a channel region (18), and a tunnel region (22). Source conductor (10) and drain conductor (12) are disposed to create inversion regions, of a second conductivity type, opposite said first conductivity type, in the source inversion region (14) and drain inversion region (16) of semiconductor layer (38) of the layer semiconductor, upon application of voltage. Thin oxide tunneling window (22) is disposed adjacent source conductor (10). A floating gate (24) disposed adjacent tunneling window can be charged or discharged by Fowler-Nordheim tunneling when a voltage is applied between the inversion created in source inversion region (14) and a control gate (26) insulatively adjacent floating gate (24).

Abstract: A method for making a NMOS self-aligned contact in CMOS circuits without an extra mask is described. The maskless contact technique makes use of the fact that the blanket N-type implant, self-aligned to exposed field-oxide edge, will not change the P+ diffusion to N-type. The net P+ concentration in the contact region is reduced slightly but does not degrade the PMOS device performance.

Abstract: Apparatus and method for production planning in a manufacturing facility is provided. The apparatus and method generates a plurality of theoretical plans and a constraint-based model for receiving one of the theoretical production plans, and applying at least one constraint thereto. Further, a cost function is computed for the theoretical production plans. Then, the apparatus and method searches for a feasible production plan among the plurality of theoretical plans, where the feasible plan is the plan which does not violate the applied constraint and has the least computed cost function.

Abstract: Apparatus for scheduling at least two concurrent transactions accessing a shared data is provided. When a lock request is granted, the apparatus provides for constructing a history file for the shared data to show each data accessing transaction, and also provides for constructing a serialization graph with each node denoting an active transaction, and each directed edge denoting a dependency between two transactions. The serialization graph is searched for a cycle formed by transactions, and if any is found, the transactions are aborted and restarted.

Abstract: One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node.

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Abstract: A method and system (10) associates a deductive reasoning system having a forward deductive reasoning portion (13), a backward deductive reasoning portion (15), and a frame template portion (18) with a constraint satisfaction system (12) within a unified framework (11). The unified framework (11) incorporates a truth maintenance system to maintain dependency between premises, rules, and consequences in the deductive reasoning system (13, 15, and 18) and between initial constraints and propagated constraints in constraint satisfaction system (12). The system (10) treats constraints as declarative statements in order to maintain logical dependency under the truth maintenance system of unified framework (11).

Abstract: A computer system includes a data processor, an address bus, a data bus, and a read only memory device interconnected with the data processor by way of the address and data buses. A random access memory device also is interconnected with the data processor by way of the address and data buses. The random access memory device includes an on-chip voltage supply, a node for connecting with a second voltage supply, and a selection circuit, arranged to be selectively enabled for supplying charge to a load circuit from either the second voltage supply or the on-chip voltage supply. Voltage V.sub.pp, applied to the load circuit from the on-chip voltage supply, has been boosted to a magnitude that is higher than the voltage V.sub.dd of the second voltage supply. Charge supplied by the combination of the second voltage supply and the on-chip voltage supply is less than the charge used by a single on-chip boosted voltage supply.

Abstract: An improved belt tensioning system 30 includes an improved tensioner 34 mounted on a fixed post 36. The improved tensioner 34 includes the body 37 having a bore 40 extending therethrough. Located in the bore 40 is an elastomeric material 42 having a Shore A durometer of between 30 and 50. Mounted within the bore 48 in the elastomeric material 42 is a bushing 44 that has a bore 46 therethrough sized to closely receive the post or shaft 36. The elastomeric material has damping characteristics capable of substantially eliminating resonant frequencies from the system. Location of the tensioner 34 on the fixed post or shaft 36 permits the appropriate tension to be applied in the system 30 and the driving auxiliary systems by the tensioner while avoiding the use of conventional belt tensioners 20 which may introduce vibrations or oscillations into the belt drive system.

Abstract: A method is provided for using a computer to select a travel route based on a selected performance criteria from a plurality of possible travel routes connecting a plurality of destinations. Information is input describing the location of each destination to be visited. For each pair of destinations, a connecting path having an optimum performance value based on the selected performance criteria is determined. An array of randomly ordered sequences is created with each sequence representing a unique ordering of the destinations to be visited. For each sequence, the optimum performance values for each connecting path of each pair of destinations are summed to obtain a total performance value for the routes described by the sequence. A genetic cellular automaton is iteratively applied to the array to determine the travel route having the selected performance criteria by computing a near optimum sequence of destinations.

Abstract: A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first portion of memory are interleaved by address with the cells of the same row of the second portion of memory. A first half of a serial register includes a plurality of storage elements that are interleaved by address with a plurality of storage elements of a second half of the serial register. Between the first and second portions of the memory cells, column leads and a multiplexer selectively couple data from either the first portion or the second portion of the columns of the memory cells to either the first half or the second half of the serial register.

Abstract: A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.

Abstract: A method and apparatus for producing optical flow obtains a first image of a first spectral region of a field of view, obtains a second image of a second spectral region of the field of view, and processes the images to obtain the optical flow of the field of view. The first and second spectral regions are non-identical, as, for example, the visible and infrared bandwidths.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).

Abstract: A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A method is disclosed for concurrency control in a system having both pessimistic and optimistic transactions, comprises the steps of entering locks on objects both for optimistic and pessimistic transactions, and validating an optimistic transaction at commit time by checking that all objects on which said optimistic transaction holds a lock have not become obsolete during the execution of said optimistic transaction. Further, a system is shown enabling optimistic and pessimistic transactions to coexist, comprising a lock table into which locks are entered for both optimistic and pessimistic transactions, a wait queue in which pessimistic transactions are entered to wait for locks held by either optimistic or pessimistic transactions, a conflict table which is referenced to determine if a lock held by a first transaction is a conflict lock with respect to a lock requested by a second transaction, and code connected to the lock table, wait queue, and conflict table.

Abstract: A mechanism and method for calendaring a plurality of events such as scheduling the operation of interrelated machines which perform a process flow. Future time is divided into segments, called buckets, of increasing length. The first two buckets are of the same size and each of the following buckets twice as large as its preceding bucket. The first bucket slides so as to always cover a specified length of time following the current time. Events scheduled in the calendar is added to the appropriate bucket, depending on how far in the future it is to take place. When the current time equals the scheduled time for an event, then that event is removed from the bucket where it resides. When a bucket has become empty because all events have been removed from it, the events in the following bucket are distributed over the two buckets preceding it.

Abstract: A method and process for computer-controlled manufacture of three-dimensional objects involves dispensing a layer of liquid, insoluble material onto a platform at predetermined locations, which then hardens. A second media, preferably water soluble, is then sprayed onto this layer to thereby encapsulate the hardened insoluble media. The uppermost surface of this encapsulant is planed, thus removing a portion of the encapsulant to expose the underlying insoluble material for new pattern deposition. After the resulting planing residue is removed, another layer of liquid, insoluble media is dispensed onto the planed surface. The insoluble media can be of any color and may vary from layer to layer, and from location within a layer to location within a layer. These steps are repeated, until the desired three-dimensional object, surrounded by a mold, is completed. At this point, the object is either heated or immersed in a solvent, thereby dissolving the mold and leaving the three-dimensional object intact.

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.