Abstract: A method and system for dynamically representing cluster analysis results. In accordance with the method and system of the present invention, a hierarchical tree is graphically displayed. The hierarchical tree represents cluster analysis of relationships between multiple items utilizing an initial distance constraint value, wherein the graphical display includes a graphically alterable threshold indicator positioned within the hierarchical tree that graphically marks the distance constraint value. The presentation of the graphical display of the hierarchical tree is dynamically altered to reflect a user-determined distance constraint value, in response to user-controlled alteration of the graphical position of the threshold indicator, such that upon changing a distance constraint for a cluster analysis, the hierarchical tree which graphically represents the cluster analysis is dynamically altered.
Type:
Grant
Filed:
November 3, 1999
Date of Patent:
April 30, 2002
Assignee:
International Business Machines Corporation
Inventors:
Jianming Dong, Shirley Lynn Martin, Paul David Waldo
Abstract: A method and apparatus for expanding a compressed list of displayed items are provided. Each item in the list is made up of a plurality of rows of pixels. When the list is fully compressed, each item is displayed by displaying only one row of pixels. The method entails using a pointer to touch the first character of an item. When that occurs, the item is expanded by displaying every other row of pixels. If the pointer touches more than one character of the item then the item will be fully expanded by having all of its rows of pixels displayed.
Type:
Grant
Filed:
December 10, 1998
Date of Patent:
April 23, 2002
Assignee:
International Business Machines Corporation
Abstract: A method of expanding an image stored in a first array including the steps of separating the first array into a plurality of rows, each row having a first plurality of data elements, each element having a value, and separately expanding each row from a first plurality of data elements in the first array to a second plurality of data elements in a second array including the steps of correlating each of the first plurality of data elements to at least one of the second plurality of data elements, and distributing the value of selected elements of the first plurality of data elements to correlated data elements of the second plurality of data elements.
Type:
Grant
Filed:
May 9, 1995
Date of Patent:
March 19, 2002
Assignee:
International Business Machines Corporation
Abstract: The method and system of the present invention provides for a test tool consisting of a Test nano Kernel and supported test programs (exercisers) which sequentially stage validity tests for central complex electronics hardware for architecture and hardware implementation for a single processor or in a multiprocessor system. Central electronics complex hardware is a processor, memory sub-system and system bridge coupled together and may include the input/output ports. Each stage becomes increasingly complex as the hardware platform becomes more stable. The Test nano Kernel consists of approximately 500 K of software code, provides multiprocessor support and implements context and 64-bit execution, effective equal to real and shared memory service, segment register attachment, gang scheduling and CPU affinity services. The Test nano Kernel provides for a smooth transition from simulation due to its capabilities to run simulation test cases on real hardware.
Type:
Grant
Filed:
February 1, 1999
Date of Patent:
March 12, 2002
Assignee:
International Business Machines Corporation
Inventors:
Theodore Joseph Bohizic, Shakti Kapoor, Walid M. Kobrosly
Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.
Abstract: The present invention provides a method and apparatus for transferring a video image, to be resized, from a host processor to an accelerator chip of a display adapter such that the storage capacity of a memory device in the chip is greatly reduced. The video data is first divided into M×M arrays of data elements. Then, the arrays are transferred one row at a time. Each row is stored before being processed by the chip. Consequently, since these rows are much shorter than the lines of frames of data elements, the storage capacity of the chip's memory device is greatly reduced.
Type:
Grant
Filed:
July 7, 1998
Date of Patent:
February 19, 2002
Assignee:
International Business Machines Corporation
Abstract: An automated software test is provided which includes a functional model of a system to be tested. The automated software test is utilized to operate a system under test in accordance with specified facts, goals and rules. Quasi-random actions are taken within the system in accordance with specified rules and facts until a defined goal has been accomplished. Training the automated software test is accomplished by specifying a particular goal, i.e. identifying a particularly known defect, and thereafter running the test in a quasi-random fashion until the particular goal has been achieved. The number and nature of actions required to achieve that goal are logged and the process is then repeated until the shortest path required to achieve that goal has been determined. The log of actions which eventually reach a particularly defect may also be utilized a probable cause tree structure for future analysis.
Type:
Grant
Filed:
January 29, 1999
Date of Patent:
February 19, 2002
Assignee:
International Business Machines Corporation
Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.
Abstract: Aspects for detecting environmental faults in redundant components of a computer system are described. In an exemplary method aspect, the method includes monitoring system environment conditions, including a status for redundant power supply and cooling components. The method further includes registering a failure condition with an appropriate error type when a monitored system environment condition exceeds a design threshold, and utilizing the registered failure condition as data in an architected error log.
Type:
Grant
Filed:
November 12, 1998
Date of Patent:
February 5, 2002
Assignee:
International Business Machines Corporation
Inventors:
Alongkorn Kitamorn, Charles Andrew McLaughlin, Kanisha Patel, Donald LeRoy Thorson
Abstract: A method for identifying predefined error conditions in a build output log file to determine if software build is defective. An output log file is generated within a storage device of a data processing system during a build of a software algorithm on the data processing system. A user creates a list file on the data processing system containing predefined valid error conditions. The output log file is searched to identify user-defined strings from the list file. A comparison of the user-defined strings identified during the search is made with predefined valid error conditions to determine when the user-defined strings identified matches the predefined valid conditions.
Type:
Grant
Filed:
December 18, 1998
Date of Patent:
February 5, 2002
Assignee:
International Business Machines Corporation
Abstract: A graphics adapter having a versatile lighting engine is disclosed. The graphics adapter generates graphics objects in a graphics scene. Each of the graphics objects within the graphics scene is made up of a number of polygons that are delimited by a set of vertices. The graphics adapter includes a graphics pipeline and a control module. In response to attributes received from a graphics software application, the control module selectively controls a frequency in which vertices are fed into the graphics pipeline and controls a number of concurrent calculations that are performed on the vertices within the graphics pipeline.
Type:
Grant
Filed:
October 2, 1998
Date of Patent:
January 22, 2002
Assignee:
International Business Machines Corporation
Abstract: A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue which holds instructions pending execution. First, a threshold level (selected maximum number of instructions in the instruction queue) is set. The current utilization measure for one or more execution units in the data processing system is determined. The current utilization measure is compared to the predetermined threshold value; and a speculative branch instruction is dispatched to a selected execution unit when the current utilization measure is less than the predetermined threshold value.
Type:
Grant
Filed:
March 12, 1999
Date of Patent:
January 8, 2002
Assignee:
International Business Machines Corporation
Abstract: A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.
Type:
Grant
Filed:
October 13, 1998
Date of Patent:
January 1, 2002
Assignee:
International Business Machines Corporation
Inventors:
Mark E. Dean, James Michael Magee, Ronald Lynn Rockhold, Guy G. Sotomayor, Jr., James Van Fleet
Abstract: A process for building a platform compliance test for only software components necessary to an application is disclosed. Initially the application is parsed to reveal only component needed for performance of the application, those components names are then checked against components names which are available to the application. A compliance test consisting of compatibility tests associated with the available components is then generated and used to evaluate platforms in which the application is intended to be developed.
Type:
Grant
Filed:
January 29, 1999
Date of Patent:
December 11, 2001
Assignee:
International Business Machines Corporation
Abstract: A method and apparatus for implementing the keys of a visual keyboard so that each key can perform multiple functions without the prior or simultaneous selection of differing visual keys. Each key is divided into quadrants each of which provide a different function which is well recognized and understood by the end user.
Type:
Grant
Filed:
April 24, 1998
Date of Patent:
December 4, 2001
Assignee:
International Business Machines Corporation
Inventors:
Hatim Yousef Amro, Miller Paul Van Eaton
Abstract: A cache replacement algorithm improves upon a least recently used algorithm by differentiating between cache lines that have been written with those that have not been written. The replacement algorithm attempts to replace cache lines that have been previously written back to memory, and if there are no written cache lines available, then the algorithm attempts to replace cache lines that are currently on page and on bank.
Abstract: A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus.
Type:
Grant
Filed:
December 10, 1998
Date of Patent:
November 27, 2001
Assignee:
International Business Machines Corporation
Inventors:
Wen-Tzer Thomas Chen, Richard A. Kelley, Danny Marvin Neal, Steven Mark Thurber
Abstract: A method and system in a computer network for the dynamic conversion of foreign language data transferred from a remote network site to a local network site into data supportive of the foreign language data, such that the data supportive of the foreign language data may be displayed at the local network site. Initially, the foreign language data at the remote network site is scanned, and individual foreign language characters are associated with the foreign language data. Next, each individual foreign language character associated with the foreign language data is mapped to a position in a table of characters capable of being transferred as data to another network site. The table and the mapping information are then transferred as data to the local network site. The characters contained in the table are subsequently automatically converted at the local network site into foreign language data. Finally, the foreign language data is displayed at the local network site.
Type:
Grant
Filed:
November 14, 1997
Date of Patent:
November 27, 2001
Assignee:
International Business Machines Corporation
Abstract: The field of the present invention is related to the transmission of data between a source device and a target device. More particularly, the present invention relates to the determination of a capacity limitation associated with the communication connection between a source device which is the source of a data transmission and a target device which is the target of a data transmission. Even more particularly, the present invention relates to determining the actual data transmission capacity of the communication connection between the source device and the target device.
Type:
Grant
Filed:
March 22, 1999
Date of Patent:
November 20, 2001
Assignee:
International Business Machines Corporation
Abstract: A method and apparatus for detecting, storing and retrieving information, including duration of view time, concerning advertisements included with Web pages seen by a particular user and thereafter using the stored information in controlling access of that user to subsequent Web pages.
Type:
Grant
Filed:
May 15, 1998
Date of Patent:
November 20, 2001
Assignee:
International Business Machines Corporation