Abstract: A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model.

Abstract: A method of and apparatus for performing blitter operations is performed in two parts. First, a description of the to-be-performed data transfer is analyzed and a computer instruction sequence is generated therefrom. The instruction sequence may include the appropriate instructions to implement scaling, clipping, and color conversion of a source image, as implicated by the blitter description. Second, the computer instruction sequence is executed an appropriate number of times, again depending upon the blitter description. One of the described embodiments transforms a blitter description that describes a target image in terms of visible rectangles into a description that describes the target image as having at least one line-type, in which the line-type comprises at least one pixel run, characterized by visible and non-visible states. The line-type description is then utilized by a code-generating logic to generate the appropriate instructions.

Abstract: In accordance with the method and system of the present invention, a local processor utilizes registers arranged in a fault/mask/cache fashion for environmental control and sensing within a data processing system. The local processor continuously reads input data from a variety of environmental sensors in order to determine if a threshold level has been reached and a fault condition exists. Cache registers allow the local processor to store/pass detailed sensor information to system firmware within system processor(s). The local processor sets a fault bit within a fault register designed to cause an interrupt to the system level firmware if any of its bits are non-zero, indicating that a fault condition has occurred. A mask register is designed to allow the interaction of both the local processor and system processor(s) when an interrupt is being serviced and help keeps track of which interrupts are being serviced and which are yet to be serviced in the case of multiple interrupt sources.

Abstract: A computer network such as the internet has servers to deliver pages of data to remote users upon demand, and these pages usually contain links to further pages. The request for data is in the form of a page address sent by the user, identifying a specific page, usually by a “URL”. The server has the ability to generate context-sensitive information about delivery of this page, including current loading at the server, transmission bandwidth for the server, and size of the data requested. The server can calculate the time needed to transfer the requested data, and send this information to the client. The user can then decide the transfer method desired, based on the information sent by the server. For example, the user may want immediate transfer, or delayed transfer, or may want to abort the request. The requested page may be sent later by email.

Abstract: A data processing system and method are described for generating virtual memory descriptors which include pretranslated physical addresses. The data processing system has a virtual memory address space and a main memory. The main memory includes a first plurality of physical addresses. A temporary association is established between a region of the main memory and a segment of the virtual memory address space. The region of main memory is addressed utilizing a second plurality of physical addresses. The segment of virtual memory is addressed utilizing a plurality of virtual addresses. In response to the establishment of the temporary association, a virtual memory descriptor is generated and is utilized to address the segment. Each of the plurality of virtual addresses is translated to one of the second plurality of physical addresses. Each translated one of the second plurality of physical addresses is stored in the memory descriptor.

Abstract: A method and apparatus is provided in which I/O data is tagged to identify an ordering of data transfer requests relative to other data transfer requests. Write and Read transaction requests are tagged for ordering relative to previous write requests. Current read and write transaction requests are selectively allowed to bypass earlier write transaction requests which have been temporarily delayed in transfer. In one embodiment, the bypass occurs in a bridge buffer positioned between I/O devices and a system memory. In another embodiment, the methodology is applied where a split read or write transaction includes reserved bits in the attribute fields which are utilized to indicate if the transaction is allowed to bypass previous write transactions.

Abstract: A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor.

Abstract: A computer controlled user interactive display system with an implementation for displaying within a defined display space a plurality of objects having dimensions proportionally representative of physical parameters of elements respectively represented by said objects, but this system is provided with a further implementation for nonlinearly modulating at least one dimension of at least one of said displayed objects so as to conform the object dimension to the dimensional limitations of the defined display space without affecting the dimensional status of the object with said modulated dimension relative to the other objects.

Abstract: An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, fb. An image of the internal bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another.

Abstract: Apparatus is provided for precisely positioning and thereafter holding a probe connected to an oscilloscope or the like. The apparatus enables a single operator to position the probe and read and adjust the oscilloscope. The apparatus has a rod like means about which a nonconducting probe holder enjoys several degrees of freedom. The rod is connected to a weighted base by a clamp through which the rod may slide as part the gross positioning of the assembly and which clamp can be adjusted to finely position the rod and probe clamp assembly.

Abstract: A method and implementing apparatus is provided which include a plurality of perceptible indicia devices which are mounted on an I/O drawer of a computer system server equipment rack. In the exemplary embodiment, the indicia devices include a light-emitting diode in combination with an alphanumeric display device. Various states of a system initialization process are indicated by different combinations of possible states of the LED and the display device such that the sequencing of a system initialization process can be traced by visual inspection of the status of the perceptible indicia devices.

Abstract: A method and apparatus are disclosed for moving one or more objects from and returning them to a user visible portion of a work plane, which includes but is larger than the visible portion, by interpreting a single user input action and in response thereto changing the position of the objects. Objects remain in the work plane in either the user visible or non-user visible portions. In one embodiment, a smaller than actual representation of the entire work plane is displayed with that portion of the work plane currently in focus by the user.

Abstract: Provided is an apparatus and method for remote retrieval of an integrated-circuit state according to the present invention uses a remote input/output (“RIO”) processor with a test circuit interface, which in the preferred embodiment is the TAP 118. The test circuit interface is for electrically-coupling to an integrated circuit having a test circuit with at least one register for storing a state-information with respect to the integrated circuit. The RIO processor executes a program that instructs the RIO processor to retrieve the state-information in response to a request command. The retrieved state information is transmitted for analysis at a location remote from the computer system using a data-and-instruction communication device.

Abstract: A method and implementing system are provided in which a service processor is implemented in addition to system processors. The service processor is enabled to access system on-chip registers to acquire system data through the use of the system JTAG bus connections. In one embodiment, logic is provided to determine concurrent calls for use of the same registers by both the system processor(s) and also by the service processor through the JTAG bus. In case of concurrent requests, the JTAG data are held so as not to interfere with system operations until the system processor's use of the registers has been completed.

Abstract: A computer controlled display system with a user interactive touch screen is provided with an on-screen mouse to which user input may be applied by rolling of the touch finger to thereby move displayed information: the pointer or scrolled information on the screen. Means are provided which are activated by the touching of the screen at any random position selected by the user for enabling the detection of any rolling of said placed fingertip in an orthogonal direction. Also provided are means responsive to the detection of said rolling of said placed fingertip for moving said displayed data in an orthogonal direction corresponding to the direction of said rolling. The data moved may be the cursor or pointer or, when scrolling, the whole screen of data may be moved.

Abstract: An apparatus and method for determining rates chargeable to advertisers based upon the actual viewing time for which their advertisements were seen by a given user. This is accomplished through the use of a advertisement control plug in combination with a file used during times in which the user is not connected to the Internet or other applicable network.

Abstract: An apparatus and method are presented for determining actual viewing times electronic advertisements were seen by a user of a Web browser or the like while viewing documents containing advertisements. A timing manager JAVA application in combination with JAVA scripts or other dynamic HTML and cookies are used in this determination.

Abstract: A tool and method that automatically formats an Engineering Change Order (ECO), in a programming language suitable for processing by an Electronic Design Automation (EDA) tool, in order to specify metal-only design changes to complex hardware data-paths through changes in the netlist. The invention comprises an initial import component that imports a working netlist which serves as the baseline on which the tool operates. The tool further comprises four components: a bus extraction component, an index creation component, a text editor, and an ECO generation component. One or more buses are extracted from the working netlist and tabulated into an index table. The user uses a test editor to modify the index table to create a modified index table that embodies the desired design change. Finally, the ECO generation component automatically reconfigures the modified index table into an ECO format in a language usable by automated physical design tools.

Abstract: A network for small businesses is provided which is easy to install, configure and operate and still provides users of the client computers in the network with the same degree of flexibility in configuring graphical user interfaces to operating systems and application programs as do present stand alone personal computers. All of the software to be used by the client computers: operating systems and application programs is stored on the network server computer. The graphical user interfaces to the operating systems and application programs are customized in the conventional manner by the users of the client computers, usually at the client computer through a conventional interactive display. In the customization of a program, the data representative of an initial user interface is stored.

Abstract: A driver circuit for use in a system that includes first, second, and possibly more power supplies. The driver circuit includes a first line driver with an output connected to a first receiver circuit and a second line driver with an output connected to a second receiver circuit. A first output enable control circuit is connected to an output enable of the first line driver. The first power supply provides an input to the output enable control circuit such that the state of the first line driver output enable is a function of the first power supply. In one embodiment, the first receiver circuit is powered by the first power supply and the second receiver circuit is powered by the second power supply. In one embodiment, the first power supply is the Vcc power supply of the system and the second power supply is the Vccsb (vcc standby) power supply of the system.