Abstract: Interrupts from an I/O subsystem are first directed to a single processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high, the interrupt is sent (offloaded) to a second specific processor. The process continues throughout all superscalar processors in the data processing system and each processor builds interrupt prediction data corresponding to the interrupt load. A threshold counter may be added to the logic so offloading does not take place until a specified number of interrupts are queued within that specific processor, thus providing a fixed level of prediction data. Some processors may be left out of the offload string so they are not disturbed by an interrupt.

Abstract: The present invention relates to a system and method for accessing television program information, particularly context sensitive information, some of which may be found through the Internet. A method and system according to the present invention is presented for interactively accessing program information on a television, the method comprising receiving a search request; generating at least one automatic search term regarding a program for television; and searching the Internet for requested information.

Abstract: Accordingly, provided is an apparatus and method for generating a computer system interrupt emulation having the effect of a hardwired interrupt. A service processor with a test circuit interface can be coupled to an integrated circuit, which has a test circuit with an access to a register of the integrated circuit. A program, executable by the processor, responds to an interrupt request by instructing the processor to save a system state of the integrated circuit and to set a system state of the integrated circuit. The method for emulating an interrupt of an integrated circuit provides for receiving an interrupt request. A register of an integrated circuit is then accessed through a test circuit of the integrated circuit. The contents of the register are saved to a storage location, and the register is then set to a state responsive to the interrupt request. The interrupt request may be made locally or remotely.

Abstract: The present invention allows advanced diagnostics to be loaded into a vehicle on demand with results being sent back to the diagnostic center, possibly requiring a more refined selection of diagnostics based on the results of the previous tests. Thus, a new generation of network vehicle communications with diagnostic centers, via cellular telephone, wireless communications and Internet access via wireless communication link, provide a rich networking topology that allows onboard computers or microprocessors to obtain problem diagnosis information and data while on the road.

Abstract: A system, method, and computer readable medium allow for granting permission to modify a memory area, such as a data variable stored in memory, without using valuable memory space to store permission variables. Rather than using separate permission variables, a portion of a data variable is used to indicate whether or not the data variable may be modified. The least significant bit of a variable (i.e. memory area) is used as a permission indicator. When the least significant bit is set to one, it is permissible to modify the variable. When the least significant bit is set to zero, it is not permissible to modify the variable. In one embodiment of the present invention, a counter variable is both checked for permission to increment, and incremented (if permission is granted) in one step. Efficiency is increased, which is especially valuable in the case of embedded systems, where memory space is typically in short supply.

Abstract: A data processing system, method, and program product for automating creation of accounts in a network are disclosed. According to the method, an account registry for a first network is accessed in response to a selected input in order to obtain account information including a plurality of usernames. The account information is then provided to an account manager for a second network that, in response to receipt of the account information, automatically creates accounts in the second network for each of the plurality of usernames.

Abstract: An active circuit for rapidly discharging stored energy in a capacitive system. The circuit is comprised of a variable impedance circuit, a voltage detector, and a time delay circuit. The variable impedance circuit includes a variable impedance output path configured to be connected between a Vcc bus of the capacitive system and ground. The voltage detector circuit includes an input coupled to the Vcc bus and an output connected to an input of the variable impedance circuit. The voltage detector circuit is configured to maintain the variable impedance output path in a high impedance condition while the Vcc voltage remains above a predetermined minimum value. The time delay circuit is coupled to the input of the variable impedance circuit and configured to maintain the variable impedance output path in a low impedance condition for a duration after the voltage of the Vcc bus drops below the predetermined minimum.

Abstract: A system and method for determining which processor is to be the master processor in a symmetric multi-processor (SMP) environment. The determination is made by boot-level code, i.e. the software program which executes first in a processor after it is brought on-line. Each processor in the SMP system is brought on-line independently of the other processors in the system, and each processor in the system can uniquely identify itself. As a processor comes on-line, it checks to see if a master processor has already been designated. If not, the processor checks to see if another processor, with a higher priority identifier, has identified itself as a working processor. If so, the processor commits to being a slave processor. If not, the processor indicates that it is available to be the master processor. A further check is made to ensure that only one processor has indicated that it is available to become the master processor.

Abstract: A multitude of devices coupled to a processor are each given a location code, which is then displayed in proximity to each of the devices. Then, when the processor indicates an error within a particular device, the service person can easily find which device has the error by the displayed location code associated with the device.

Abstract: Polling of devices on an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device.

Abstract: A method and implementing computer system is provided in which PCI CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA conventions are maintained in a large computer system and each PCI Host Bridge (PHB) CONFIG.sub.-- ADDRESS register and each PHB CONFIG.sub.-- DATA register have separate and system-unique addresses. In one example, the operating system provides a service to translate the device driver's configuration operation to a particular bus and device in the system, to a particular CONFIG.sub.-- ADDRESS or CONFIG.sub.-- DATA register of the PHB which has that device under it. By using this method, the hierarchical system can use architecture-independent routing of addresses down to the PHB that contains the appropriate CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA registers.

Abstract: A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus.

Abstract: A method and apparatus for coupling a user-created window, or object, to menu functions of another application is accomplished once functions of another program have been selected and an attachment menu bar is created. The attachment menu bar is then graphically attached to the user-created object. When one of the selected menu functions is invoked, the system performs the function indicated by the selected function on an object within the user-created object or on the user-created object.

Abstract: A method and apparatus is provided in which a site selection program is operable to selectively initiate sample testing of data transfer speed of a plurality of sites containing a predetermined data file. The methodology calculates a priority ordering of the plurality sites based upon the sample testing of data transfer speed, and divides the data file into portions for parallel access and delivery of the requested data file such that all of the portions are delivered to the user at approximately the same time, whereby faster channels will be requested to access and deliver larger file portions and relatively slower channels will be assigned to access and deliver relatively smaller portions of the requested data file. Upon receipt of the portions, the requested data file is assembled for further processing by the user.

Abstract: A method and apparatus for detecting and initializing the addition of a new client machine to a network while requiring only minimal intervention by an individual. The above is accomplished by using the unique network adapter addresses, for each client of the network, to determine whether or not existing client machines are operative, as well as the addition of a new client machine to the network. Upon the detection of the addition of a new client machine, the new client machine is initialized using profiles and templates to default parameters, and is fully operative with minimal interaction by an individual.

Abstract: An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, f.sub.b. An image of the 60x bus is produced, operating at a lower frequency of operations, f.sub.o, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY.sub.-- and SHD.sub.--, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be "out-of-phase" with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another.

Abstract: A method and implementing computer system is provided in which a network file system is operable to report multiple virtual files in various formats for a single native file in storage. When one of the files is opened, the file system reads data from the single native file and converts the format on the fly to the destination format that was opened by the operating system. The operating system thus converts files spontaneously on request and provides a synthetic file in a desired one of a plurality of possible formats while requiring the storage of only one native content file in server memory. Further aspects of the file system include provisions for additional features including Directory, Open File, Read File, Write File and Seek operations.

Abstract: A method and implementing computer system is provided in which a function or applet for example may be downloaded from a network server and graphical user interface (GUI) processor interprets a data stream consisting of GUI controls and attributes, and places the controls and attributes in a presentation space. In an exemplary embodiment, a web browser program loads an HTML (Hypertext Markup Language) from a GUI (Graphical User Interface) stream processor applet from a web server. The web browser then loads the GUI stream processor (GSP) from the web server and begins executing the GSP. The GSP then requests the GUI stream from the web server by opening a stream to a file, CGI (Common Gateway Interface) script or servlet on the server. The GSP then receives the GUI stream and assembles the user interface in the JAVA applet presentation space managed by the browser. The GSP may periodically update itself by repeating the last two steps.

Abstract: A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.

Abstract: A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock.