Abstract: A shared peripheral controller including a primary bus interface, a primary bus first register, a shared bus interface, and a control unit. The primary bus interface is adapted to receive an operation via a primary bus, such as an ISA bus, from a first processor, such as a PCI-to-ISA bus bridge. The shared bus interface is adapted to communicate with a first shared peripheral, such as a real time clock, via a shared bus. The control unit is coupled to the primary bus interface and configured to detect a first segment of a first operation issued by the first processor to the first shared peripheral. The control unit is further configured to buffer the first segment in the primary bus first register until the control unit detects a second segment of the first operation whereupon the control unit is configured to issue the first and second segments of the first operation to the first shared peripheral in consecutive cycles of the shared bus.

Abstract: A system and method for compressing state transition data on a computer system is disclosed. The method and system include separating the state transition data into a plurality of segments and separating each of the plurality of segments into a plurality of subsegments. The method and system further include providing a plurality of code words. Each of the plurality of code words corresponds to a unique subsegment of the plurality of unique subsegments. The method and system also include providing a representation of each segment. The representation of each segment includes a portion of the plurality of code words. The portion of the plurality of code words replaces the plurality of subsegments in each of the plurality of segments. Thus, the present invention allows compressed state transition data to be used without full uncompression, allowing a system to be explicitly checked without substantial loss of information and without consuming memory.

Abstract: A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.

Abstract: A system is provided for the configuration of operations in a network comprising at least a server computer and a respective plurality of client computers connected to each server computer. The system involves the combination of means for interactively prompting a user to make a sequence of data entries, each of said entries being apparently unrelated to computer operations and covering a demographic aspect of the business environment using the network, and means for allocating network computing components and operations among the computers in the network in response to and based upon said user entries. All of the programming resources which are allocated may be found in the server and the algorithms for allocating and distributing are also on the server. The allocation of programs by the server computer is based upon user profiles for each user developed as a result of the data entries made in response to the above-described prompt panels.

Abstract: A method and system for deconfiguring software in a processing system is disclosed. In one aspect, a processing system comprises a central processing unit (CPU), and a memory coupled to the CPU. The memory includes a memory array and a memory controller for capturing information concerning the status of the memory array. The processing system includes a service processor for gathering and analyzing status information from the memory controller. The processing system also includes a nonvolatile device coupled to the CPU and the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the memory array from the service processor. The deconfiguration area also provides information for deconfiguring at least a portion of the memory array during a boot time of the processing system. Accordingly, through the present invention, memory errors are detected during normal computer operations by error detection logic.

Abstract: Primary and secondary servers are coupled together for furnishing a backed-up video streaming function for outputting a series of video content presentations to a user group. The primary server functions as the primary provider of the video files and the secondary server is arranged to operate as a “hot stand-by” to back-up the primary server. In the event the primary server is disabled, the secondary server takes over for the primary server in furnishing video content in accordance with a common playlist. When the secondary server goes down for any reason, the illustrated methodology effectively re-synchronizes the video content and the video stream of the secondary server with that of the primary server such that the secondary server is enabled to resume the back-up function without interruption of the video file streaming process being carried on by the primary server.

Abstract: A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

Abstract: An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto.

Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.

Abstract: Two daughter cards connected by bus connectors to a motherboard have integrated circuits connected to each other and to an integrated circuit on the motherboard through a bus network. The bus network is also connected by a bus cable connected at the top of the two daughter cards so as to form a loop within the bus network.

Abstract: An apparatus and method of dynamic resource mapping for isolating interrupt sources is implemented. Each interrupt source is provided with a unique identifier. The identifier is mapped to an interrupt number which is sent to an operating system when the interrupt source corresponding to the identifier generates an interrupt. Each device is associated with a data structure that includes a data value which is operable for accessing an interrupt register. The data value may be a pointer that points to a pointer to the interrupt register for the device generating the interrupt. When an interrupt is generated, the mapping may be used to access the pointers which thereby provide direct access to the interrupt register, whereby the contents of the interrupt register are processed by an interrupt service routine.

Abstract: A padded wrist rest that is integral with a portable electronic device, meaning that the wrist rest is sold with the device and does not have to be removed from the device to close and store the device, is disclosed. While integral to the portable electronic device, the wrist rest of the present invention can be removed by the user or owner of the portable electronic device for maintenance or replacement. The wrist rest may be single- or multiple-part, and includes one or more pads manufactured from encapsulated gel, closed-cell foam, fabric-covered padding, vinyl-covered padding, or leather-covered padding. The wrist rest may include one or more bases that are slid, screwed, or snapped into place on the portable electronic device.

Abstract: A bus bridge coupled between primary and secondary busses including a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to a read request transaction from the first peripheral device while leaving transactions in the second buffer set unaffected. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate mastership of the secondary bus and the source of a subsequent transaction to be received via the secondary bus. The bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus.

Abstract: A system and method for managing mirrored logical volumes are provided wherein a user designates one mirror of a given logical volume, having a first entry point, as the backup mirror, with a different entry point, for that logical volume; and thereafter, upon user issuance of an I/O command, appropriately valid mirror(s) are selected to be read from or written to as a function of which of the two entry points to the same data is specified.

Abstract: A command string is sent from an operating system to a microcontroller coupled to one or more I2C buses. Such a command string may instruct the microcontroller to perform a read or write operation with respect to a bus device designated within the command string. The presence of the bus device may be new and the microcontroller unaware of such a presence. Data may be read from the main system to the particular bus device through the microcontroller, or data may be read from the bus device through the microcontroller back to the main system.

Abstract: A system, method, and computer readable medium for eliminating unnecessary ring transitions is described. Often, a requested system service or I/O operation can be performed entirely at a higher ring level, such as Ring 3, with no need to transition to a lower ring. In these cases, the software interrupt or I/O instruction which generates the ring transition is replaced by a call to a program executing at the higher ring level. Thus, the software interrupt instruction or I/O instruction is redirected to code that resides at the same protection level and emulates the effects of the instruction, resulting in improved execution speed. In the Intel 80×86 family of microprocessors, both the software interrupt instruction and the I/O instruction take two bytes to encode. It is thus possible to replace the instruction with the op-code for a segment:offset far call, letting the instruction stream dictate the offset for the call.

Abstract: A computer system including a chassis of substantially rectangular cross section suitable for receiving a circuit board. A rear face of the chassis includes upper and lower exhaust ports. A CPU board including one or more processors may be housed within the chassis. The expansion board is suitable for receiving a plurality of expansion cards via connectors attached to the board. The expansion board includes at least one void for facilitating air flow and is housed within the chassis wherein a rear side of the board is proximal to the rear face of the chassis between the upper and lower exhaust ports. An air moving device is positioned within the chassis for directing air flow across the expansion board toward the rear face of the chassis and, via the at least one void in the expansion card, through the upper and lower exhaust ports.

Abstract: The present invention provides a method for allowing a user's reading to dictate the speed and position at which content is converted to audio in an audio reader. The method includes determining a position of a user's eye gaze, identifying a content displayed at the position of the user's eye gaze, determining an audio corresponding to the content, and outputting the audio. The method of the present invention allows the user's reading to drive the text to speech conversion, resulting in the computer reading what the user is currently reading. The user may then read text at a variable rate and at different positions, with the text to speech conversion following the user. The method of the present invention may be used to help raise users' literacy levels, to help users learn to read faster, to help boost reading comprehension, to help users scan documents, and to provide feedback for positioning and control. The present invention is thus flexible and has a range of utilities.

Abstract: A method and apparatus for displaying to a user attributes of a computer workstation includes a processor, user controls for controlling a pointer, a display device, and a database. The processor first displays a template area on the display device and then retrieves the attributes of the computer workstation from the database. After retrieving the attributes, the processor displays icons representing the attributes in the template area displayed on the display device.

Abstract: A speech recognition system which interprets speech queries such as help queries and presents a list of relevant proposed commands sorted in order based upon relevance of the commands. The system organizes the displayed commands being prompted to the user through probability determining means which for each of a predetermined plurality of speech commands store an associated set of speech terms, each term having relevance to its associated command combined with means responsive to a speech query for determining the probability of speech terms from said set in said query, and means responsive to said probability determining means for prompting the user with a displayed sequence of commands sorted based upon said probability of speech terms associated with said commands. When such a sorted command is selected, the system has means responsive to a speech command for carrying out the system action corresponding to the command.