Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

Abstract: A multiplexer circuit for programmable logic devices (PLDs) has reduced susceptibility to single event upsets. The pass gate multiplexer circuit has 2N pass gates and N memory cells controlling the pass gates. Each path between an input terminal and the output node includes two pass gates controlled by different memory cells. Therefore, a single event upset that inadvertently enables a pass gate can only short two input terminals when the other pass gate in the affected input path is also enabled by its associated memory cell. Therefore, the multiplexer circuit with two pass gates in each input path reduces the susceptibility to single event upsets by a factor of (N−4)/N.

Abstract: Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD.

Abstract: A method and apparatus to accelerate the evaluation of complex, computationally intense digital signal processing algorithms is disclosed. In one embodiment, a filter accelerator is connected in parallel with a conventional digital signal processor (DSP). The accelerator enhances the speed at which the DSP performs some filtering operations by calculating and maintaining a number of partial results based on a selected number of prior data samples. Each time the DSP receives a new data sample for filtering, the DSP makes use of one or more partial results from the accelerator to speed the calculation of the filtered result. Receipt of the new data sample causes the accelerator to recalculate the partial results, this time using the new data sample. The accelerator thus prepares for receipt of the subsequent data sample, freeing the DSP to perform other operations.

Abstract: Counter-based duty cycle correction (DCC) circuits and methods. A first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in a register. Thus, the value stored in the register represents a point halfway through the input clock period. Each time the input clock signal changes from a first state to a second state, an output clock generator also changes the output clock signal from the first state to the second state, and the second counter is enabled. A comparator compares the value in the second counter to the value stored in the register. When the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached, and the output clock generator changes the output clock signal from the second state back to the first state.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract: After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal.

Abstract: A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.

Abstract: A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

Abstract: A method and apparatus for implementing fast sum-of-products logic in a Field Programmable Gate Array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice.

Abstract: A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a specified permission bit or bit pattern in the permission memory block before the core will operate. If the permission bit or bit pattern is set properly, the core functions correctly when implemented in the PLD. If not, the core will not function. To prevent the customer from modifying the core such that it no longer depends upon the permission bits to function, the configuration bitstream used to program the PLD can be encrypted before and during transmission to the PLD. This encryption ensures security of the customer's logic design as well as the supplier's core design. In this manner, the customer remains dependent upon properly set permission memory bits, i.e. proper authorization, to obtain core functionality.

Abstract: A clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.

Abstract: An IC package provides structural rigidity to a flexible substrate, but still allows access to mounted capacitors after package assembly. In a flip chip package, the IC die is mounted face down on a flexible laminate substrate. A metal lid is mounted above and in contact with the die. The metal lid includes openings over portions of an outer region of the substrate to accommodate the capacitors. However, portions of the metal lid extend to the corners of the substrate to provide structural rigidity to the flexible substrate. Some embodiments are directed to packages configured as described above, but in which an IC die has yet to be mounted.

Abstract: In a plurality of logical device driver instances, each instance (201) representing a specific version (220) of the device driver, can be accessed by an embedded application (200) via a common interface (205). A logical device driver instance includes the common interface which includes a plurality of functions (206-209) linked to the embedded application. A logical device driver also includes a virtual function table (211) having pointers (212-215) that points from each of the plurality of functions of the common interface to a plurality of functions (221-224) of a specific version of the device driver among a plurality of versions of the device driver. The virtual function table is set up dynamically during run-time initialization of a logical device driver instance.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Abstract: A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.