Abstract: A method of designating circuit element positions using uniform coordinate systems that can be applied to non-uniform logic arrays. A “site map” is constructed comprising a uniform array of “sites”. A uniform coordinate system is applied to the site map. The various logic blocks, which may be of different types and sizes, are mapped to the site array. The result is the imposition of a uniform coordinate system on a non-uniform logic array, using the intervening abstraction of a site array. Because the site array is uniform, a relative location constraint applied to a site within the site array retains its validity regardless of the location of the site within the site array, even when the relative location constraints are normalized.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

Abstract: A tester to device-under-test interface is disclosed in which a PCB has a socket for a device under test (DUT), one or more cable connectors for cables from an IC tester, an interface matrix card slot having a plurality of contacts electrically connected to the DUT socket and the cable connector pins, and an interface matrix card having a plurality of horizontal and vertical conductors capable of being electrically connected to each other for mapping the proper connection of signals between the DUT socket and the tester cables.

Abstract: A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. In a first mode, the DLL circuit counts and stores a first number of delays necessary to synchronize the two signals. In some embodiments, the circuit also stores a second value representing the number of unit delays in one clock period. In a second mode, the DLL circuit uses the first stored value to add the correct number of unit delays to the input clock signal. In some embodiments, the second stored value is used to generate phased output signals.

Abstract: Two-dimensional discrete wavelet transform analysis and synthesis banks. In various embodiments, a cascade combination of two one-dimensional wavelet transforms is implemented, along with a set of memory buffers between the two stages. The memory buffers store intermediate results between the stages of the two-dimensional discrete wavelet transform, thereby eliminating off-chip memory references.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.

Abstract: Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

Abstract: Method and apparatus for routing input signals having different voltage requirements in a PLD circuit design. In various example embodiments, the input signals are grouped into logical clusters, wherein the input signals in each logical cluster have a common input voltage standard. Input pins of the device are grouped into physical clusters, wherein each physical cluster is associated with a voltage standard. Each of the physical clusters is paired with a logical cluster and has associated therewith one or more programmable logic elements as determined by the input signals to be routed to the programmable logic elements. For each paired logical cluster and physical cluster, the input signals of the logical cluster are routed from the pins of the physical cluster to the programmable logic elements of the physical cluster.

Abstract: Methods for designating target locations for circuit elements to be implemented in a programmable system. A target system is divided into blocks at various levels of hierarchy, with each block within the same higher-level block having a different identifier. A user can specify a desired location for a circuit element at any or all of these levels of hierarchy. Preferably, a desired location is specified using a single location constraint comprising a string of identifiers separated by delimiters. In one embodiment, a uniform coordinate system is applied to all blocks at a given level, even in a non-uniform programmable array. In this embodiment, a non-uniform array of logic blocks is divided into tiles, and a uniform coordinate system is applied to the tiles. Thus, any tile in the array can be addressed using a uniform coordinate system, regardless of the nature of the logic blocks comprising the tile.

Abstract: Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or other logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.

Abstract: An input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The adjustable trip point is provided by a trigger circuit. A control circuit determines whether the trigger circuit is on or off by comparing a configuration input thereof with a reference power supply input thereof. When the trigger circuit is on, the trip point is active during a low to high transition of the signal input.

Abstract: Methods and structures for implementing wide multiplexers in programmable logic devices (PLDs) in a distributed fashion. According to one embodiment, a configurable logic structure includes a function generator, a carry multiplexer, and an OR gate. The function generator is configured to implement a multiplexing function (under control of a first select signal) and an AND function (ANDing the output of the multiplexer with a second select signal). The carry multiplexer is configured to perform an AND function between an output of the function generator and a third select signal. Thus, with three select signals available, an 8-to-1 multiplexer can be implemented by combining the outputs of four different logic structures that use different values of the select signals. This combination of outputs is performed by forming an OR chain, with the OR input of each stage being provided by the associated carry multiplexer.

Abstract: A system and method for developing a circuit design for a programmable logic device. A tool is provided for interactively modifying a configuration bitstream, downloading the bitstream to a programmable logic device (PLD), and reading back and displaying state information from the PLD. In one embodiment, the tool is command driven. Responsive to a first command, the tool implements a selected logic core from a library of run-time parameterizable logic cores in a configuration bitstream. The bitstream can be automatically downloaded to the PLD as part of the first command, or alternatively, using a separate command. A second command is available for applying a clock signal to the PLD. After application of the clock signal, the states of selected elements implemented by the logic core are reported.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.