Abstract: Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDS, a single event upset can short together two module output signals and render two of the three voting circuit input signals invalid. The invention addresses this issue by providing quintuple modular redundancy (QMR) for high-reliability circuits implemented in PLDs. Thus, a single event upset that inadvertently shorts together two PLD interconnect lines can render invalid only two out of five module output signals. The majority of the five modules still provide the correct value, and the voting circuit is able to correctly resolve the error. In some embodiments, a user selects a high-reliability circuit implementation option and/or a PLD particularly suited to a QMR implementation, and the PLD implementation software automatically implements the QMR structure for the user circuit.

Abstract: A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Abstract: A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.

Abstract: A method is provided for watermarking FPGA configuration data. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a design file containing a marked macro received from the macro vendor, rather than the actual macro. The end user then uses an FPGA programming tool to convert the design file into configuration data. Specifically, the FPGA programming tool processes the design file to detect marked macros. If a marked macro is detected, the FPGA programming tool embeds a watermark corresponding to the macro within the configuration data.

Abstract: An EEPROM memory cell array architecture (50) that substantially eliminates leakage current to allow for reading memory cells (20) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor (26). On one embodiment, the ground transistor (26) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor (26) and the memory cell=s read transistor (32). In another embodiment, the ground transistor (26) is a low voltage transistor controlled by a separate low voltage control signal.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2 P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

Abstract: A one-shot circuit provides a pulse on receipt of a first edge, and removes the pulse after a delay generated by a delay chain. However, a second, opposite edge resets the circuit without an intervening delay chain delay. The delay chain can be implemented using a chain of AND circuits (one-shot high) or OR circuits (one-shot low), each driven by the preceding circuit in the chain and by the input signal. In some embodiments, an output circuit includes a pass gate coupled between the one-shot input and output terminals and a pulldown (one-shot high) or pullup (one-shot low) that provides an inactive value when the pulse is not being applied. The pass gate and pullup or pulldown are controlled by the output of the daisy chain. Other embodiments offer programmable capabilities, such as the ability to correct for process shift by altering the effective delay of the delay chain.

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Abstract: Efficient register circuits allow the loading of data values into a memory element using set and reset terminals in addition to loading via the data input terminal. A register circuit includes a memory element and a logical AND gate. A load command input terminal enables the load, and a load value input terminal provides the new value to be loaded. The memory element has set and reset terminals. In one embodiment, the reset function overrides the set function when both terminals provide active signals. The set terminal is coupled to the load command input terminal. The logical AND gate has input terminals coupled to the load command and load value input terminals, and an output terminal coupled to the reset terminal of the memory element. In another embodiment, the set function overrides the reset function, and the signals driving the set and reset terminals are reversed.

Abstract: A method of generating a test bit pattern for a memory device is provided. The method includes, for example, the steps of loading a data register with an initial test bit pattern and storing the initial test bit pattern in the memory device. The method also includes the steps of generating a additional test bit patterns by shifting the initial test bit pattern by a predetermined number of bits and storing the additional test bit pattern in the memory device. The step of shifting the initial test bit pattern includes, for example, the step of pushing a one or two-bit pattern into the initial test bit pattern. Subsequent successive test bit patterns are similarly generated by pushing a one or two-bit pattern into the previously generated test bit patterns. Hence, the number of bits loaded into the data register is greatly reduced and the required test bit pattern still generated.

Abstract: Methods of detecting shorts affecting nets of a specified design in a partially defective PLD. The nets participating in the design are identified, along with the interconnect lines used to implement each net. The nets are then divided into two or more groups, where no two nets in a single group can be shorted together by the inadvertent enablement of a single programmable interconnect point between two interconnect lines. The groups are then tested for inadvertent shorts. According to a first aspect of the invention, each group is tested sequentially against all interconnect lines not in the group, or against all nets in other groups. According to another aspect, the groups are tested simultaneously by applying a different stimulus pattern to each group. By comparing a detected value pattern to the stimulus patterns applied to other groups, it can be determined which two groups are participating in the short.

Abstract: A one-dimensional wavelet system and method. In various embodiments, computation engines are set forth for forward and inverse transforms in a wavelet system. The computation engine includes a plurality of register banks having input ports arranged to receive input sample values and a multiplexer coupled to the output ports of the register banks. A processing unit is configured to perform the forward or inverse wavelet transform for data values that are sequenced through the register banks and multiplexer by a control unit. The computation unit is adaptable to implement discrete wavelet transform, discrete wavelet packet, and custom wavelet trees.

Abstract: A power on reset (POR) generator circuit includes a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage. During a fast power up, the capacitor on the bandgap output signal ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit helps to prevent glitches from reaching the POR output signal by raising the voltage on the internal node after the reference voltage is exceeded. Various embodiments include programmable logic devices and systems that include the described circuits.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models.

Abstract: The invention provides methods for marking packaged ICs. In a first embodiment, only the minimum performance information is first marked on the package, regardless of the actual performance of the IC. This method avoids a second marking step for all ICs sold as low-performance ICs. In another embodiment, only one inking and curing step is required for all ICs. According to this method, all specified performances are marked on the packaged IC at the first marking. The IC is then tested to determine the actual performance, and all performance markings not applicable to the IC are removed, preferably with a laser. Alternatively, all applicable performance markings are identified (e.g., underlined or enclosed with a laser marking).

Abstract: A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.

Abstract: Programmable circuit structures having reduced susceptibility to single event upsets. A circuit structure includes a programmable circuit controlled by a group of memory cells, of which at most one has an enable value. The memory cells are coupled together such that if any one memory cell in the group is at the enable value, then all other memory cells in the group are forced to a disable value. If a single event upset occurs at any of the disabling memory cells the value in the memory cell does not change, because the memory cell is being held disabling by the one enabling memory cell. However, if a single event upset occurs at the enabling memory cell, causing it to become disabling, a circuit error occurs. Thus, the susceptibility of the circuit structure has been reduced by a factor of (N−1)/N, where N is the number of memory cells.

Abstract: A configurable logic block for a programmable logic device includes a storage element having a latch clocked by a write strobe pulse. The storage element uses a write strobe signal and, optionally, a hold signal already present in the CLB. In one embodiment, the CLB includes a function generator, a write strobe generator providing hold and write strobe signals to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator. Because the CLB already includes a write strobe generator, it is not necessary to design additional logic to avoid race conditions in the storage element.

Abstract: A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.

Abstract: A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.