Abstract: A driver circuit drives heavily loaded signals at high speeds with a reduced crowbar current. One-shots are used to drive the output pullup and pulldown, thereby minimizing the period when both devices are turned on. One embodiment includes an inverter, a one-shot low, a one-shot high, a pullup, and a pulldown. An input signal drives the inverter and the two one-shots. The inverter output terminal is coupled to the driver output terminal, as are the pullup and pulldown. The one-shot low circuit controls the pullup. The one-shot high circuit controls the pulldown. Another embodiment includes two pre-driver circuits, one controlling an output pullup and the other controlling an output pulldown. Each of the pre-driver circuits is implemented using a one-shot low and a one-shot high, as described above. One such embodiment is an output driver for a PLD, and the one-shots include various programmable options.

Abstract: Described are a method of programming a programmable logic device using encrypted configuration data and a programmable logic device (PLD) adapted to use such encrypted data. A PLD is adapted to include a decryptor having access to a non-volatile memory element programmed with a secret decryption key. Some or all of the decryptor can be instantiated in configurable logic on the FPGA. Encrypted configuration data representing some desired circuit functionality is presented to the decryptor. The decryptor then decrypts the configuration data, using the secret decryption key, and configures the FPGA with the decrypted configuration data. Some embodiments include authentication circuitry that performs a hash function on the configuration data used to instantiate the decryptor on the PLD. The result of the hash function is compared to a proprietary hash key programmed into the PLD. Only those configuration data that produce the desired hash result will instantiate decryptors that have access to the decryption key.

Abstract: A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic.blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.

Abstract: Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the interconnect lines of the PLD, two routed nodes are separated from each other by at least two programmable interconnect points (PIPs). Therefore, if a single event upset causes a PIP to become inadvertently enabled, the affected node is coupled to an unused interconnect line, instead of to another node within the circuit. In some embodiments, a triple modular redundancy (TMR) circuit is implemented. Signals in one module are separated from signals in another module by at least two PIPS. However, signals within the same module can be separated by only one PIP, because the TMR structure of the circuit can compensate for errors within a single module.

Abstract: A novel method and corresponding system are provided for safely reconfiguring a portion of a reprogrammable logic device. The method includes the steps of identifying the nets to be reprogrammed, identifying the device drivers that may induce signal contention during or after a new configuration on the identified nets, electrically isolating the identified drivers, and implementing the new configuration.

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract: A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.

Abstract: A method and apparatus for testing software having a user interface are presented in various embodiments. The method generally entails evolving a test sequence by generating random test actions. A test sequence is created by assembling a set of interface components associated with an interface window. One of the interface components is randomly selected, and a random action is generated to apply to the interface component. The test sequence is documented by recording data that identifies the interface component and the action, and the action is then applied to the user interface.

Abstract: A multiplexer circuits for programmable logic devices (PLDs) reduced susceptibility to single event upsets. The pass gate multiplexer circuit has N input circuits having pass gate and N memory cells controlling the pass gates. Each path between an input terminal and the output node includes two pass gates controlled by different memory cells. Therefore, a single event upset that inadvertently enables a pass gate can only short two input terminals when the other,pass gate in the affected input path is also enabled by its associated memory cell. Therefore, the multiplexer circuit with two pass gates in each input path reduces the susceptibility to single event upsets by a factor of (N−4)/N.

Abstract: Structures and methods that reduce interconnect resource usage and routing delays in FPGAs by routing high fan-out signals on the CLB carry chains. In a first embodiment, a high fan-out signal distribution structure is implemented in a Field Programmable Gate Array (FPGA). The FPGA includes an array of logic cells, each including a carry multiplexer. The carry multiplexers can be configured to form a carry chain. The carry chain is used to distribute high fan-out signals by passing a high fan-out signal along the chain from carry-in terminal to carry-out terminal, and tapping the signal at the carry-out terminals for distribution to a large number of destinations.

Abstract: A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is minimal, and is independent of the divisor. Variations include programmable divisors and multipliers and optional phase shifting.

Abstract: A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay.

Abstract: A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: A method of configuring FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

Abstract: A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

Abstract: A system and method for translating a report file to a constraints file is provided. A circuit design is initially generated to be implemented on a logic device and a report file corresponding to the logic device is created. To transfer the circuit design to a different logic device, a constraints file generator analyzes the report file to determine characteristics of the logic device. A compatibility logic identifies a compatible device to the logic device based on the characteristics. A constraints file is then generated in accordance with the compatible logic device such that the circuit design can be re-targeted to the compatible device.