Abstract: A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power supplying voltage is lower than a certain level and in response to the pumping enable signal during an auto refresh operation; and a high voltage generating unit for generating a high voltage by performing a pumping operation in response to the auto refresh pumping enable signal.

Abstract: A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for controlling the first and the second delay lines, and turns off the second signal processor after DLL locking. The DLL circuit further includes a phase comparator for generating a comparison signal notifying which of phases of a first clock signal of the first delay line and a second clock signal of the second delay line precedes the other, and a signal selector for inputting an output of the second signal processor to the second delay line before the DLL locking, and inputting the comparison signal of the phase comparator to the second delay line after the DLL locking.

Abstract: An impedance matching circuit includes a code generating unit for generating a calibration code in response to a reference voltage and a voltage on a node, a calibration resistance unit for supplying a power supply voltage to the node, being calibrated to an external resistor, wherein the calibration resistance unit includes a switching unit for turning on/off a plurality of resistors connected in parallel in response to the calibration code, a termination pull-up resistance unit provided at an output node for receiving the calibration code, wherein the termination pull-up resistance unit has a switching unit which is identical to that of the calibration resistance unit, and a termination pull-down resistance unit at the output node, for receiving the calibration code, wherein the termination pull-down resistance unit has a switching unit which is identical to that of the calibration resistance unit.

Abstract: A semiconductor memory device includes a plurality of column circuit units selectively operated with a burst length set in a mode register set. A plurality of column control blocks control column access to unit cells, each block activated by each of plural column control signals, and a column control signal generator outputs the plural column control signals to the plural column control blocks in response to a column access command and a burst length.

Abstract: Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.

Abstract: A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.

Abstract: A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a signal at an intersection of the system clock signal and a reference signal; a third input unit for generating a third clock signal based on a signal at an intersection of the inverted system clock signal and the reference signal; a delay unit for generating a delay clock signal by delaying the first clock signal in response to a delay control signal; and a clock delay control unit for generating the delay control signal in response to a phase difference between the second clock signal and the delay clock signal or a phase difference between the third clock signal and the delay clock signal.

Abstract: A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.

Abstract: A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal clock which is selected by the multiplexer, a phase detector for comparing a phase of the first internal clock with that of a feedback clock which is feedbacked from the delay means to thereby output a comparing signal, a low pass filter (LPF) mode generator for outputting a locking signal, which checks a locking state of the feedback clock based on the comparing signal and a first and a second control signals, to the delay means, and a low pass filter for receiving the comparing signal to inform whether or not the comparing signal is erroneous to the delay means.

Abstract: A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.

Abstract: A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD, when the equalization signal is repeated by a repeater. In order to improve bit line precharging performance of the bit line precharge portion enabled by the equalization signal, a rising interval of the equalization signal is activated as the boost voltage. Precharging is then performed with the external supply voltage after a predetermined time period. Thus, a thin gate insulating membrane can be used in a transistor in the bit line precharge portion which receives the equalization signal can be formed.

Abstract: A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the DLL being in a delay locked state; and an output enable signal generating unit for generating a plurality of output enable signals in response to the DLL clock and outputting a final output enable signal in response to the select signal.

Abstract: A semiconductor memory device includes decoding units for decoding input address signals efficiently. The semiconductor memory device includes a predecoding circuit, a first main decoding circuit, and a second main decoding circuit. The predecoding circuit predecodes address signals. The first main decoding circuit decodes output signals of the predecoding circuit, thereby outputting first decoding signals to a first bank. The second main decoding circuit decodes output signals of the predecoding circuit, thereby outputting second decoding signals to a second bank.

Abstract: An internal address generator for use in a semiconductor memory device includes an address detector, a drive pulse generator, and a delay unit. The address detector generates a comparison signal by comparing a first address currently input with a second address previously input. The drive pulse generator generates a drive pulse in response to the comparison signal. The delay unit outputs the first address as the second address and delays the second address to thereby generate an internal address synchronized with the drive pulse in case that the first address is different from the second address.

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract: A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit.

Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

Abstract: There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an initial synchronizing unit for outputting a first output enable signal when a read CAS signal is activated; a plurality of synchronizing units connected in series to output an output signal of a previous stage as an output enable signal in synchronization with a corresponding driving clock, a first stage of the synchronizing units receiving the first output enable signal; and a test unit for adjusting a delay amount of an input clock according to a test signal and outputting the driving clock.

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract: An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal according to the enable signal and generate a peripheral voltage according to the enable signal.