Abstract: A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.

Abstract: A process for forming isolation slots having immunity to surface inversion comprises the steps of defining a slot region in a semiconductor substrate, implanting dopants in the substrate adjacent the mouth of the slot which have conductivity types appropriate to counteract inversion across the filled slot, applying a spacer layer over the exposed surface of the layers defining the slot and over the substrate, etching the spacer layer to leave spacers only along the edges of the materials defining the slots and etching the substrate to form the slots.

Abstract: A temperature compensated differential level shift circuit is provided. An ECL type buffered differential circuit employs a source of threshold voltage, V.sub.T, which matches the temperature-dependent characteristic of the input section of the level shift circuit. In a preferred embodiment, a Schottky diode is provided in the output section of a bandgap reference voltage generator which matches the temperature dependence of a Schottky diode in the input section of the level shift circuit. As temperature shifts, the threshold voltage will shift in a manner that tracks the temperature-produced shift in the input voltage as it passes through the Schottky diode in the input section of the level shift circuit. Matched PNP or NPN transistors may also be used in the input section of the level shift circuit and in the output section of the bandgap reference voltage generator.