Abstract: A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.

Abstract: A method for programming an analog/multi-level flash memory array, which insures fast programming to substantially all of the cells in the array, without over-programming, is based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes three stages which program and verify cell threshold voltages with different program verification margins so that an accurate cell threshold voltage can be achieved for each cell.

Abstract: A controlled-gain amplifier has a gain control port responsive to a control voltage Vc, and produces a gain proportional to Vc raised to a fixed or continuously variable power X, such that gain=K(Vc).sup.X, where K is a constant. Precise gain control is achieved through the use of pulse width modulation (PWM) control of cascaded amplifier stages. A PWM regulator linearly controls the gain of each amplifier stage, and multiple stages are cascaded for (Vc).sup.N gain control, where N is an integer. One or more amplifier stages may contain a variable low pass filter that allows continuous control of the control exponent to produce non-integer exponents. The circuit can be used as a Sensitivity-Time-Control (STC) circuit in sampling-type radar systems, or in ultrasonic rangefinders, where the gain of the receiver needs to increase exponentially with increasing range.

Abstract: The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors.

Abstract: Systems and methods are described for providing low-voltage triggering electrostatic discharge (ESD) protection in the context of integrated circuits. A low-voltage triggering electrostatic discharge protection circuit has a low trigger voltage and can turn on quickly to provide a low resistance path. The protection circuit can be employed in power bus, input, and input/output pin ESD protection configurations. This protection circuit is compatible with complementary metal oxide semiconductor (CMOS) processes. High ESD performance can even be achieved with devices fabricated in accordance with advanced CMOS processes.

Abstract: A system and method for assembling or generating content addressable video based on storing a plurality of frames of video data at addressable storage locations. Each frame of video data is stored with a tag which indicates the contents of the video image defined by the associated frame. For assembly, a processing unit assembles a content video image in response to the tags; the content video image, including positions for corresponding frames of video data. Finally, a means, such as a look up table, is provided for associating the positions in the content video image with addresses of storage location storing the corresponding frames of video data. A user input device is provided by which the user selects a particular frame of video data, by selecting a position in the content video image, such as by positioning a cursor on the selected position.For generating content addressable video, the content video image is first generated.

Abstract: The present invention provides a method and an apparatus for programming a selected call within a virtual ground EPROM array cell without disturbing adjacent array cells.

Abstract: The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input.

Abstract: An atomic type switch mesh is combined with standard local area network links, such as high speed Ethernet, and a bridge-like protocol to provide a high performance scalable network switch. The network switch comprises a plurality of switch nodes, a first set of communication links which are coupled between switch nodes internal to the network switch, and a second set of communication links which comprise network links from switch nodes on the border of the network switch to systems external to the network switch. The respective switch nodes include a set of ports (having more than two members) which are connected to respective communication links in either the first or second set of communication links. Each port in the set comprises a medium access control (MAC) logic unit for a connectionless network protocol, preferably high speed Ethernet.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources.

Abstract: A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.

Abstract: A high power, highly efficient laser that produces a polarized, round diffraction limited gaussian beam is disclosed. A strong thermal lens laser crystal with controlled ellipticity, is mounted in a laserhead and pumped by a fiber-bundle-coupled diode source. The pump beam diameter in the crystal is greater than the crystal's TEMOO mode diameter. The laser operates well over a large range of pump powers. Its slope efficiency in the TEMOO mode is greater than 40%, with an overall efficiency greater than 25%. One of the lasing crystals used is Nd:YVO4. This material exhibits high gain and a short upper state lifetime. These properties make it attractive in designing a Q-switched laser, or one that is insensitive to optical feedback.

Abstract: An actuator for controlling alignment of an object that is characterized by an alignment plane, such as mirrors used in optical cavities, comprises a mounting frame, and a one piece alignment member formed of piezoelectric material having a first end and a second end that is secured to the mounting frame at the second end. On the first end, a first object contact, a second object contact, and a third object contact are secured defining an object plane. A means is provided for holding the object in contact with the first, second and third object contacts so that the alignment plane of the object has a predetermined relationship with the object plane defined by the object contacts on the tubular member. Electrodes are formed on the tubular member for establishing an electrical field between the surfaces of the alignment member so that the positions of the first object contact, second object contact and third object contact are controlled.

Abstract: A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.

Abstract: A multi-layer graded reflectivity mirror (GRM) with high effective reflectivity is suitable for use in large aperture laser systems with relatively low gain. The GRMs are manufactured with multiple dielectric layers with a thickness profile that eliminates the interference fringes, while providing a reflectivity which tapers smoothly from a peak to zero. The mirror is formed on a substrate having a first surface and a second surface opposite the first. The substrate consists of a material which has low absorption at a given wavelength .lambda.. A first dielectric layer is formed on the first surface of the substrate which has an index of refraction n.sub.1 and having an optical thickness profile with a maximum optical thickness of .lambda./4 at a center which essentially continuously decreases away from the center to a minimum optical thickness of Z at a perimeter P. A second dielectric layer is formed on the first dielectric layer having an index of refraction n.sub.

Abstract: A disposable fiber diverter probe is provided that eliminates many of the typical problems associated with conventional fiber diverter probes that are designed to be used multiple times and must be sterilized between each use. The present invention utilizes thermoplastic materials in many of the components that traditional designs require to be made of metal in order to perform the required functions of a fiber diverter probe. The improved design of the present invention enables less complex, low cost parts to be used in a fiber diverter probe, wherein the probe still provides expanded capabilities over conventional, more expensive fiber diverter probes, such as more accessible and user-friendly controls for the surgeon. Moreover, the reduced cost of the fiber diverter probe provided by the present invention enables a medical facility or a private physician to make disposable fiber diverter probes economically feasible, thus eliminating the risk of exposing patients to a contaminated probe.

Abstract: A device for resolving deadlock between a local processor and system resources for access to a local store in a multiprocessor data processing system having high speed cache comprises an address storage device, deadlock resolution logic and a deadlock detector. The address storage device is coupled to the local bus for storing addresses in response a local store access signal on the system bus and for supply of the address to the cache controller. The detector is connected to the local bus and system bus to detect a deadlock condition. The deadlock resolution logic generates a sequence of control signals in response to the deadlock signal that resolves the deadlock condition. In particular, deadlocks are resolved by tristating the local buffer in response to the deadlock signal to disable external access signals from controlling the local bus to allow a local store access signal to gain control of the local bus.

Abstract: In a centrally controlled resource arbitration system, each of the units concurrently requesting access sends its identity code and the binary complement thereof to a central arbitration processor. The identity codes are logically combined into a first word, and the binary complements are logically combined into a second word. A subset identifier of the requesting units is then formed by combining corresponding bits of the first and second words. Unresolved values in the subset identifier are iteratively removed to eliminate a subset of the requesting units. When all but one of the requesting units have been eliminated, access to the resource is given to the remaining unit.

Abstract: An apparatus for storing data for read and write access receiving reset control signals, comprising a plurality of storage blocks, each block including an array of memory units for storing a unit of data is provided that is reset along storage block boundaries. A reset control means, coupled to receive the reset control signals which identify at least one of the storage blocks, is included for generating block reset signals. A means, coupled to the memory units in each storage block and to receive the block reset signals, for resetting the identified block of memory to 0. .