Abstract: A voltage detector circuit of a nonvolatile memory integrated circuit for determining the voltage potential of a supply voltage is provided. The voltage detector includes a first MOS device, a second MOS device, a bias circuit for adjusting the current through the first and second MOS devices that is responsive to the level of the supply voltage, and an output circuit that provides an output signal indicating the level of the supply voltage. The bias circuit may comprise a voltage divider circuit which provides a predetermined ratio of the supply voltage to the gate of one or both of the MOS devices. The voltage divider circuit may comprise MOS devices configured as resistive devices in series. The current through the MOS devices is provided to the output circuit, and the output circuit utilizes a measure of the difference in the current levels to determine the level of the voltage supply and provide the appropriate output signal.

Abstract: A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.

Abstract: A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and operable in parallel with the registered address path.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.

Abstract: An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included.

Abstract: An equivalent time pulse-echo radar or other pulse-echo system employs a transmit reference sampler collocated with the transmitter to provide a transmit reference pulse, which initiates a pulse width modulated (PWM) pulse. A receive sampler connected to a receive antenna provides an echo-detection pulse that terminates the PWM pulse, such that the width of the PWM pulse indicates target range. The transmit reference sampler and the receive sampler are driven from a common clock such that transmit-receive timing offset drift precisely cancels on a picosecond scale, thereby enabling sub-mm range accuracy with common, low-cost circuit elements. The radar further includes automatically referenced pulse detectors that are responsive to either the magnitude or the phase of the sampler outputs. The radar can be used for precision tank level measurements, robotics, or automotive ranging applications.

Abstract: A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line.

Abstract: A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and silicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

Abstract: The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

Abstract: An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.

Abstract: An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.

Abstract: A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic.

Abstract: A circuit generates a power on reset signal in response to the changing of a supply potential across a supply node and a reference node from a power down level to a power on level. The circuit comprises a capacitor having a first terminal coupled to the supply node and a second terminal. An output driver, such as an inverter, is coupled between the supply node and the reference node. The output driver has an output coupled to the second terminal of the capacitor. An input driver comprises a circuit which drives the input of the output driver to a level which tracks changes in the supply potential. A clamp transistor, such as a n-channel MOS transistor having a lower threshold than normal transistors in the circuit, is coupled between the input of the output driver and the supply potential. The clamp transistor clamps the input of the output driver to a driver ready level which is below the trip point of the output driver when the supply potential is at a power down level.

Abstract: A game play system allows remote players to participate in a concurrent simulation of a live event as the live event is occurring. The system gathers input from sensors located at the live event, preprocesses this input, and transfers it to a computer system, which uses this input to create a concurrent simulation of the live event. A remote game player can then interact with the concurrent simulation by providing input to the concurrent simulation through a user interface. This system combines the excitement of a highly interactive video game with the drama and publicity surrounding a live event. The live event can thereby set the standard of performance for the concurrent simulation. Remote game players may additionally compete against each other to determine an overall global winner amongst the remote game players in the live event.

Abstract: A method and device for programming multiple levels of voltage states in a memory cell. A program and verify memory cell device includes a memory cell coupled with at least one dummy cell, the devices sharing common drain, gate, and source nodes. The threshold voltage of each dummy cell is set to a target threshold level for programming the memory cell. A stair-step sequence of pulses is used to program and verify the memory cell. A constant current source can also be coupled between the source node and the ground. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then applying program and verify pulses at the memory cell gate.