Abstract: A logic circuit communicating to and from an input/output port in a variety of input modes and in a variety of output modes. The circuit may be configured to have a dedicated, registered, or latched input; and in the output mode to have a registered, combinatorial or latched output. A register/latch, in conjunction with a programmable input select multiplexer, can function as an input, output or buried register or as a transparent latch. A programmable clock select multiplexer selects between a clock/latch enable signal applied at an external pin or a product term generated internally. Clock polarity control is also provided. Asynchronous reset and preset of the register/latch is provided along with polarity control therefor. Dedicated and programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The logic circuit can be deployed in banks, each bank electably receiving the same or a different clock.

Abstract: Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.The pointer directs memory accessing to prevent conflicts.

Abstract: Disclosed is an improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: The present invention provides a single stage crossbar and a controller for controlling the crossbar that provides a capacity for "wide-sense non-blocking" connection of input signals to outputs that exceeds the number of outputs to which a given input is connected. Thus, the capacity of the crossbar is increased using a smaller number of crosspoints in a single stage than was available in the prior art.In one aspect, the present invention is an apparatus for connecting a signal on one of a plurality of inputs to a non-busy one of a plurality of outputs, comprising a plurality of controllable switches arranged so that each input is connectable to at least an integer q outputs and so that no two inputs share more than an integer c outputs. The invention further comprises a controller for controlling the controllable switches to connect the signal to a non-busy output so that no more than an integer f outputs that are connectable to any input become busy, where f is less than q.

Abstract: An integrated circuit having multiple programmable arrays in which a first programmable array receives a plurality of first inputs and generates a plurality of first outputs as programmed by the user. Also, a second programmable array receives a plurality of second inputs and generates a plurality of second outputs as programmed by the user. Also, buried state registers store signals as programmed by the user. An input multiplexer selects and supplies the first and second inputs from a variety of sources, including the first and second outputs, the buried state registers and I/O pins. An output multiplexer selects and supplies output signals to a set of output pins from a variety of sources, including the first and second outputs and the buried state registers.

Abstract: A programmable event generator for generating digital timing waveforms in response to a triggering signal includes one programmable read-only memory for storing and outputting data words corresponding to the digital timing waveforms and next address words to address another of the data words, a storage register for temporarily storing and outputting any one of the data words and next address words, another mapping programmable read-only memory for storing and outputting starting address words to start the addressing of the one programmable read only memory, a multiplexer to select either a starting address word or a next address word to address the one programmable read-only memory, and a programmable control circuit, responsive to the triggering signal, for clocking the storage register at a programmed clock frequency.

Abstract: In assigning features to nodes of a tree structured classifier and determining terminal nodes in response to a training set of objects each being determined by a plurality of features, a selected characteristic, such as a cost function based on the minimum description length, of the plurality of features unused at prior nodes is determined along the path from the root to the present node, a feature is then assigned to the node having a preferred value for the selected characteristic relative to the other features. Child nodes of the node are created in response to the assigned feature with features assigned thereto in a similar way. The preferred values for the selected characteristics of the assigned features for the child nodes of the node are combined and compared with the preferred value of their father node. Classification of the father node as a terminal is based upon such a comparison.

Abstract: In a distributed processing system network in which at least one node operates as a source location having access to data objects of a database, and at least one other node operates as a replica location storing replicas of data objects from the source location, managing obsolescence of the replicas is performed by having the replica locations submitting requests to the source location for ascertaining obsolescence of data objects. The source location, responsive to a request from a requesting replica location, extracts identifiers of a set of obsolete objects and communicates them to the requesting replica location. Upon receiving the identifiers, the requesting location renders inaccessible those data objects corresponding to the identifiers received. The source location then removes those identifiers that have been communicated to the requesting replica location.

Abstract: In a distributed processing system having a source node accessing data objects from a database and a replica node storing replicas of requested source data objects received from the source location, the impact to replicas caused by a change in a source data object is calculated by assigning a version number to the change. An identifier of the portion of the source database affected by the change is generated, as well as a list of replicas containing objects from the affected portion of the database. For a replica location communicating with the source location, a table of the replicas from the list is then recorded along with the version number for communicating to the replica location.

Abstract: An improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: Disclosed is a method for recording a record that emulates a first recording format, which includes a track reference point, such as an index field, used for determining a position of a record on a track according to the first recording format, on a moving storage device operating according to a second recording format which also includes a track reference point. The invention comprises the steps, responsive to location information generated according to the first recording formats, of:(1) determining an original angular position of a record according to the first recording format;(2) calculating in response to the original angular position and a parameter a preferred angular position for the record according to the second recording format;(3) determining an actual angular position of the record recorded according to the second recording format; and(4) recording an extension of the record to compensate for the difference between the preferred angular position and the actual angular position.

Abstract: Disclosed is an apparatus for synchronizing a first signal with a second signal comprising a plurality of delay means D.sub.i as i goes from 1 to N, where N is an integer, each delay means D.sub.i having an input I.sub.i and a delay output O.sub.i for delaying a signal received at the respective input I.sub.i by an increment .delta.t of time in supplying the delayed signal at the respective delay output O.sub.i. The first delay means D.sub.1 of the plurality of delay means is connected to receive the first signal at its input I.sub.1. Each of the other delay means D.sub.i, for i equal to 2 to N, are connected in series such that the respective input I.sub.i is connected to receive the delay output O.sub.i-1 of the preceding delay means D.sub.i-1. A plurality of latch means L.sub.i, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L.sub.i latches the signal at the delay output O.sub. i respectively for each of the delay means D.sub.

Abstract: An apparatus for generating an output signal having a selected output polarity. The apparatus comprises a sensing means for generating a logic signal upon occurrence of an event. Also, a programmable means generates a programmable signal indicating a selected output polarity. The logic signal and the programmable signal are received by polarity setting means for producing an output signal equal to the logic signal with the selected output polarity. Also disclosed is a testing means for temporarily forcing the programmable signal to indicate a selected output polarity for testing.

Abstract: The present invention discloses a low order charge-pump filter operable with a single variable current source. The integrating capacitor of the charge-pump is connected in an H-bridge switching configuration with four switches that are operable to control the current source to supply current to a first node of the capacitor or to a second node of the capacitor or to bypass a capacitor, depending on the state of operation of the charge-pump. The charge-pump filter disclosed is particularly useful for providing the low order response for a phase detector in a phase-locked loop.

Abstract: Disclosed is a digital phase-locked loop circuit for telecommunication circuits receiving bipolar codes. The digital phase-locked loop circuit includes a transition timer means for counting a transition duration between a high mark and a low mark in said bipolar code. A clock recovery signal is generated by dividing a transition duration by a value, such as two, to indicate an apparent zero crossing time, and comparing the apparent zero crossing time with the reference clock in the circuit receiving the bipolar code. The reference clock in the receiving circuit is adjusted in response to the clock recovery signal in order to maintain the reference clock substantially in phase with the incoming bipolar code.

Abstract: Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.

Abstract: Disclosed is a circuit providing a controllable effective resistance which comprises of transistor means that provides current at an input node responsive to an input voltage at the input node. The transistor means is coupled to a settable current source which operates to control the effective value of the controllable effective resistance. The invention also includes a filter which employs the controllable effective resistance to vary the breakpoint frequency of the filter. Also, a phase-locked loop apparatus employing the filter is disclosed.

Abstract: A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.

Abstract: The fall-time of an ECL gate is precisely controlled using a fixed capacitor, which is connected between the positive supply voltage and the ECL gate output terminal, and a variable current source connected between ground and the ECL gate output terminal. A time-delay circuit is obtained by controlling the variable current source with an error voltage of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates with controlled fall-times in a ring oscillator configuration. Addition of a non-inverting input to one ECL gate makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function.

Abstract: A standard ECL OR/NOR gate is modified to have a single current source connected to the load current source transistors. The single current source is connected to the emitters of each of the load current source transistors. Switching between the two load current source transistors is accomplished by connecting the base of at least one of the load current transistors to a circuit point that tracks the opposite phase. In one embodiment the base of one of the load current source transistors is connected to the common emitter connections of the input transistors and the reference transistor while the base of the other load current source transistor is connected to a reference voltage source V.sub.BBL having a value intermediate the extreme values which appear on the common emitter connections of the input transistors and the reference transistors.