Abstract: A method system for reporting error logs in a logical partition computer system is disclosed. Error logs reported for the computer system are stored in an error log partition. An event scan routine is instantiated for each of the logical partitions that make requests to read new error logs in the error log partition. In response to receiving a request from each of the event scan routines, the new error log is retrieved for the respective event scan routines. Once it has been determined that each of the logical partitions have read the new error log, the new error log is marked as ready for deletion in the error log partition.

Abstract: A method, system, and apparatus for customizing procedures to be performed during an initialization process in a data processing system is provided. In one embodiment, a class of procedures to omit during the initialization process is determined. This class of procedures may be for example, the omission of identifying and creating nodes for a certain class of drives, such as, for example, all ssa drives. Once procedures to omit from the initialization process are determined, then all other initialization procedures are performed except, of course, for the procedures belonging to the class of procedures determined to be omitted.

Abstract: A method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions fetched by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during fetching of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions fetched is known from the fetched instructions information stored in the trace storage device. Hence the instruction stream may be reconstructed from the information stored in the trace storage device.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A system and method are disclosed for visually indicating a usage of a magnetic tape that is included in a magnetic tape cartridge. The apparatus includes a take-up spindle for receiving magnetic tape when the magnetic tape is moving in a forward motion. The apparatus also includes a meter assembly having a meter coupled to the take-up spindle. In a first embodiment, the meter is incremented only in response to each full rewind of the magnetic tape. In a second embodiment, the meter is incremented in an amount that is directly proportional to the amount of each rewind of the tape.

Abstract: A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction history field, a next line address field, and a data field. The prediction history field provides information about the success of past data cache address predictions. The next line address field provides information about the predicted next data cache lines to be accessed. The data field provides data to be used by the processor. When a data line in the data cache is accessed by the processor, determines the value of a prediction history field and the value of a next line address field. If the prediction history field is true, then the next line address in the next line address field is prefetched. Based on whether the next line actually utilized by the processor matches the next line address in the next line address field, the contents of the prediction history field and the next line address filed are modified.

Abstract: A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A normalization circuit suitable for use in a graphics adapter is disclosed. The circuit is configured to receive vertex data and includes a set of multiplexer circuits, a set of functional units, and a control circuit. The outputs of the set of multiplexer circuits provide inputs to the set of function units and the control circuit is configured to control the select inputs of the set of multiplexer units to calculate a unit normal vector and a unit eye vector from the received vertex data. The set of functiontional units may include a pair of floating point multipliers and a floating point adder. The inputs of the first floating point multiplier may be connected to outputs of first and second mulitplexers such that the first multiplier is enabled to generate square values for x, y, and z components of the vertex data. The inputs of the floating point adder may be connected to outputs of third and fourth multiplexers, wherein the floating point adders is enabled to generate a sum of squares values.

Abstract: A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.

Abstract: A floating point exponentiation circuit suitable for calculating the value BE is disclosed where B and E are floating point values. The floating point exponentiation circuit includes circuitry for producing a value P, where P is approximately equal to E*((BEXP−127)+log2(1.BMAN), BEXP is an exponent field of the base B, and 1.BMAN is a 24-bit mantissa field of the base B. The floating point exponentiation circuit further includes circuitry for adjusting the value P wherein the floating point representation of the adjusted value of P includes a mantissa field that indicates an integer portion Pi of P and a fractional portion Pf of P.

Abstract: A method and system for transmitting video data are disclosed. The method includes receiving a first video image and comparing the first video image to at least one stock image where each of the stock images is associated with a corresponding index value. If a match between at least a portion of the first video image and one of the at least one stock images is detected, the index value corresponding to the matching stock image is transmitted over a transmission medium. In one embodiment, the method further includes receiving the transmitted index value and generating the corresponding stock image from the index value. The method of may further includes comparing the first video image with a set of stock images. If it is determined that the first image does not match to any of the set of stock images, then a new index value is assigned to the first image and the first image is added to the set of stock images.

Abstract: A method and apparatus in a data processing system for asynchronous context switching. Requests of graphics processes are received to process graphics data for display in a queue in the graphics adapter. A current context is switched for a first graphics process to a new context for a second graphics process only in response to requests received in the queue. In this manner, the graphics adapter is able to continuously process commands in the queue instead of waiting for new commands to be sent after each context switch.

Abstract: A method and system comprising at least one service processor that is connected to memory and a host system. Additionally, the host system includes at least one host input resource device, such as, for example, a floppy disk, and an interface connecting the host input resource device to the service processor. The interface provides a means for the host input resource device to update, restore, or initialize host system parts or images. In one embodiment, this invention disconnects the host input resource device from main system power and connects it to auxiliary standby power. Thus, the host input resource device makes possible a less costly, less burdensome update of any piece of a data processing system.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: A method and an apparatus is presented for updating flash memory that contains a write protected code, a first copy of rewritable recovery code, a second copy of rewritable recovery code, and a rewritable composite code. Each block of rewritable code contains a checksum code to detect if the block of code has been corrupted. If it is detected that the first copy of the recovery code is corrupted then the second copy of the recovery code is copied into the first copy of the recovery code. If it is detected the second copy of the recovery code is corrupted then the first copy of the recovery code is copied into the second copy of the recovery code. The recovery code is responsible for checking and updating the composite code. If it is detected the composite code is corrupted then a fresh copy of the composite code is obtained from a removable storage device or a network connection.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: A method and apparatus for detecting bits set in a data structure. A first level encoding stage receives bits for the data structure, groups the bits into a set of bit groups, and encodes the set of bit groups to form a set of output bits. A set of intermediate level encoding stages is connected to the first level encoding stage. Each level intermediate encoding stage receives output bits from a previous stage, groups the output bits into a plurality of bit groups, and encodes the plurality of bit groups to generate a plurality of output bits. A final level encoding stage is connected to a last intermediate level encoding stage within the set of intermediate level encoding stages, wherein the final level encoding receives final output bits from a last intermediate level encoding stage within the plurality of intermediate level encoding stages and encodes the final output bits to generate an indication of bits set in the data structure.

Abstract: A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block.

Abstract: A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.

Abstract: Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.