Abstract: A method of and software for booting a network computer with universal boot code is disclosed. Initially, the type of a boot device is determined from among a set of possible boot devices. A command in a high level boot code segment of the boot code software is then translated to a command executable by the boot device based upon the determined device type. The converted command is then executed on the boot device to transfer data between the network computer and the boot device. The boot code is preferably compatible with a variety of boot devices including a hard disk boot device, an NFS server boot device, as well as a TFTP server boot device. In an embodiment in which the boot device is a TFTP boot device, a READ command from the high level boot code is translated to a TFTP read request. The data transferred by the TFTP read request may be stored in a file cache on the network computer.

Abstract: An apparatus, method, and system for determining the shape of a three dimensional object. In a preferred embodiment, the apparatus includes an array of sensors and elastic connections between the sensors within the array. When placed over a three dimensional object, the array of sensors deforms to conform to the surface topology of the three dimensional object. The sensors are connected to a data processor in which the data from the sensors is taken to construct a three-dimensional representation of the actual physical three dimensional object.

Abstract: A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.

Abstract: A method and system for problem determination and fault isolation in a storage area network (SAN) is provided. A complex configuration of multi-vendor host systems, FC switches, and storage peripherals are connected in a SAN via a communications architecture (CA). A communications architecture element (CAE) is a network-connected device that has successfully registered with a communications architecture manager (CAM) on a host computer via a network service protocol, and the CAM contains problem determination (PD) functionality for the SAN and maintains a SAN PD information table (SPDIT). The CA comprises all network-connected elements capable of communicating information stored in the SPDIT. The CAM uses a SAN topology map and the SPDIT are used to create a SAN diagnostic table (SDT). A failing component in a particular device may generate errors that cause devices along the same network connection path to generate errors.

Abstract: A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.

Abstract: In one aspect of the invention, an assembly includes an optical-electronic die having electrically conductive pads and a submount with first and second opposing sides and a third side essentially perpendicular to the first submount side. The first and third submount sides have an adjoining edge, with electrically conductive pads on the first submount side bonded to the die pads, second electrically conductive pads on the third side of the submount, and electrically conductive traces interconnecting the first and second submount pads. The conductive traces are formed on the first and third sides and adjoining edge of the submount by a process that uses a shadow mask.

Abstract: Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address to a corresponding instruction in memory. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

Abstract: A method and apparatus in a data processing system for searching for documents. A first thread is initiated, wherein the first thread provides an interface with a user to manipulate the results returned by the second thread. A search request is received. A second thread is initiated, wherein the second thread performs a search using the search request and stored in the results in a data structure and wherein the first thread and the second thread are executed in parallel in the data processing system.

Abstract: A method, system, and computer program product for emulating a sequence of events resulting from user interaction with an applet in which the storing and retrieval of queued event objects is facilitated through the use of an index to a component vector. When an applet event recorder is invoked and the applet selected, an automator initializes the applet and generates a component vector that includes a reference to each component of the applet. Events are then detected by the applet event recorder via automator listeners. The automator then generates queued event objects and stores the queued event objects in an automator queue. The generation of queued event objects in one embodiment includes the generation of a component index value that points to the component of component vector that references the applet component that was responsible for generating the corresponding user interaction event.

Abstract: A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

Abstract: A method and apparatus in a data processing system for processing perspective transformations. An estimate of a depth coordinate is obtained. A determination is made as to whether the estimate is sufficiently accurate for the perspective transformation. An algebraic operation is performed on the estimate if the estimate is insufficiently accurate for the perspective transformation, wherein the algebraic operation increases the accuracy of the estimate.

Abstract: Apparatus and methods are provided to perform volume rendering via composited texture-mapped convex polyhedra. This is accomplished by generating a sequence of z polygons defined by the intersection of a sequence of z planes parallel to the view plane with the convex polyhedron. The vertices of the convex polyhedron are numbered sequentially based on z-axis depth and this defines a sequence of slabs that are bounded by z planes intersecting the vertices. The edges of the convex polyhedron are numbered based on viewing the polyhedron along an axis from the closest vertex to the furthest vertex. A data structure maintains a list of active edges for each slab, where an edge is “active” if the edge intersects any z plane in the slab. Each vertex in the z polygon is defined by the intersection of an active edge with the z plane. The z polygon is rendered by connecting adjacent vertices, where the ordering is determined by the order of the active edges in the slab.

Abstract: A method and system for servicing an interrupt is presented. An interrupt handler associated with a detected interrupt is invoked, and a determination is made as to whether to instantiate a delay before further servicing of the detected interrupt. If a delay is neccesary before the detected may be fully serviced, a delay counter is initialized to a first predetermined value. The interrupt handler then exits without fully servicing the detected interrupt. During subsequent invocations, the interrupt handler decrements the delay counter and checks whether the delay counter has reached a second predetermined value. The interrupt handler is repeatedly invoked while the interrupt remains pending and while the delay counter does not equal the second predetermined value, the interrupt handler may then fully service the interrupt and clear the interrupt.

Abstract: A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned system, from accessing data from a memory location allocated to another OS image is provided. The system includes logical partitions, operating systems (OSs), memory locations, I/O adapters (IOAs), and a hypervisor. Each operating system image is assigned memory locations and input/output adapter is assigned to a logical partition. Each of the input/output adapters is assigned a range of I/O bus DMA addresses by the hypervisor. When a DMA operation request is received from an OS image, the hypervisor checks that the memory address range and the I/O adapter are allocated to the requesting OS image and that the I/O bus DMA range is within the that allocated to the I/O adapter. If these checks are passed, the hypervisor performs the requested mapping; otherwise the request is rejected.

Abstract: A method and system for controlling access to an adapter, such as a graphics adapter, are disclosed. The method includes querying an adapter lock with a first thread. Thereafter, responsive to determining that the lock indicates the first thread does not have access to the adapter, a sequence to obtain access to the adapter is initiated where the sequence includes writing the adapter context corresponding to the first thread. The, sequence may include a ring 3 to ring 0 transition. The method also includes, in response to determining that the lock indicates the first thread has access to the adapter, communicating to the adapter with the first thread without invoking the sequence to obtain access to the adapter. In one embodiment, querying the adapter lock includes writing a first word of the adapter lock using an atomic operation.

Abstract: A frame buffer system includes a first frame buffer containing a first set of pixels, and a second frame buffer containing a second set of pixels. A first register is connected to an output of the first frame buffer, wherein the first register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A second register is connected to an output of the second frame buffer, wherein the second register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A selection logic is connected to the first frame buffer and to the second frame buffer. The selection logic selectively selects pixels to be read from the first frame buffer and the second frame buffer into the first register and the second register. A multiplexer has a first input connected to an output of the first register, a second input connected to an output of the second register, and an output configured for connection to a digital to analog converter.

Abstract: A method, system, and computer program product for reducing a boundary of a subspace in a binary space partitioning tree is provided. In one embodiment a space containing an object for which an image is to be rendered and displayed to a user is divided into subspaces. The boundaries of each subspace are recalculated to remove at least a portion of the dead space from within the subspace. The recalculation is performed by analyzing the spatial extent of the object or objects within the each subspace and recalculating the boundaries of each subspace to be coextensive with the boundaries of the object or objects within the subspace.

Abstract: A method for locating a defective component in a data processing system during system startup is disclosed. Each component within the data processing system is assigned a location code. Then, a progress code is associated with a location code and a function being loaded to, tested, or executed in a component. After supplying power to the data processing system, the components of the data processing system are initialized and tested to establish a configuration. During the initialization and testing, a location code of a component and a corresponding progress code are displayed on a display panel. In response to a system hang, a defective component can be identified utilizing the location code and the progress code displayed on the display panel.

Abstract: The present invention is a mechanism for providing redundancy in the instruction buffer of a microprocessor such individual entries which test bad during manufacturing can be tolerated and the baseline specification of the microprocessor can be met. The present invention utilizes the instruction allocation logic of a microprocessor to allow additional buffer entries, above those called for in the specification to be provided. More particularly, each buffer entry is tested and the results are used to identify which individual entry or entries have a defective operational status. This information is then used to update the instruction allocation logic such that functional entries are considered for allocation, while those entries that test bad can be avoided. Further, the test status information can be used to set a “manufactured good” bit in the entry itself. This bit is then read ultimately by the allocation logic and instructions can be allocated accordingly, i.e.

Abstract: A method and apparatus in a geometry engine having a plurality of stages for processing graphics data. An immediate mode data stream is received at a first stage within the plurality of stages. Data from the immediate mode data stream is stored in a storage to build a vertex data structure for processing within the plurality of stages. The vertex data structure is transmitted to the first stage for processing in response to receiving a signal to transmit the vertex data structure. Data for the vertex data structure remains in the storage as default data for a subsequent vertex data structure.