Abstract: A method and apparatus in a data processing system for processing graphics data. A set of clip areas defining a window for use in clipping graphics data is identified in which a portion of the graphics data is obscured. A clip area in a first hardware clipper is set, wherein the clip area encompasses the window to process the graphics data. The graphics data within the first clip area is graphics data to be displayed. A no clip area is set in a second hardware clipper, wherein the no clip area encompasses the portion and wherein which graphics data in the second clip area is to remain undisplayed. The graphics data is sent to the first hardware clipper and the second hardware clipper.

Abstract: A method, apparatus, and computer implemented instructions for managing a plurality of caches of data, wherein the data processing system includes a plurality of independent computers. In response to initiating a read operation to read data on a data block, an indication is posted on a directory of data blocks identifying the computer that now holds a copy of that block and a location in the memory of that computer where a flag associated with that block is held. Then in response to initiating a write operation on that data block, messages are sent to all the computers holding that block which resets the said flag, thus informing each computer that the data in that block is no longer valid. These messages are sent using means that perform that flag reset without, in the preferred embodiment, any overhead of interruption of processing on the computers where the flags reside.

Abstract: A mechanism is provided for predicting cache array bit line or driver failures. This mechanism checks for five consecutive errors at different addresses within the same syndrome on invocation of event scan polling to characterize the failure. Once the failure is characterized, it is reported to the system for corrective maintenance including dynamic and/or boot time processor deconfiguration or preventive processor replacement.

Abstract: A method, apparatus, and computer implemented instructions for processing an error in a multiprocessor data processing system. An error is detected within the data processing system. A chip, causing the error, is identified within a plurality of chips to form an identified chip. Data is collected from the identified chip and hardware associated with the identified chip.

Abstract: An open format storage subsystem and method are provided. The storage subsystem and method include at least one host endnode, at least one processing unit endnode, and at least one storage endnode. These endnodes are partitioned according to partition tables assigned to the ports of the endnodes and partition keys assigned to queue pairs of the ports. Based on these partition keys, partitions in the storage subsystem are designated. In this way, certain endnodes may be designated as being able to communicate with only certain other ones of the endnodes. Because of the partitioning mechanism of the present invention, an open format storage subsystem is formulated such that the types of endnodes in the storage subsystem are not limited to vendor specific units. This enhances the ability to add and remove units from the storage subsystem by removing the limitations typically found in closed storage subsystems.

Abstract: A method, system, apparatus and computer program product are disclosed for screening electronic messages, wherein a sentry determines whether electronic messages to a receiver include respective passes from the receiver. Responsive to such a message having a pass, the receiver is notified about the message. Responsive to the message not having a pass, a notice for the sender is generated about a pass for the message. Ultimately the pass is generated and sent, on behalf of the designated receiver of the message, to the sender. Unless the sender of the electronic message receives the pass which was returned to the sender by a screening agent for the designated receiver, and the sender returns the pass to the receiver, then the screening agent discards the message and the receiver will not ever be burdened with the message.

Abstract: According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.

Abstract: In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.

Abstract: A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus.

Abstract: A branch prediction method includes the step of retrieving prediction values from a local branch history table and a global branch history table. A branch prediction operation is selectively performed using the value retrieved from the local branch history table when the value from the local branch history table falls within first predicted limits. A branch prediction operation is selectively performed using the value retrieved from the global branch history table when the value from the global branch history falls within a second predetermined limit.

Abstract: A method, program, and system for modifying computer program instructions during execution of those instructions are provided. The invention comprises writing a first instruction into a memory location, wherein the instruction is a patch class instruction. This first instruction is then fetched from the memory location and executed. Concurrent with execution of the first instruction, the memory location is overwritten with a second instruction, which is also a patch class instruction. Because the first and second instructions are patch class instructions, if a program is executing from the memory location, or returns to execute from that location, it will fetch and execute either the first instruction or the second instruction. In one embodiment, reconciling the processor's execution pipeline with the memory location will ensure that the second instruction is fetched and executed if the program returns to execute from that location.

Abstract: A method, system, and product are described for configuring remote input/output (RIO) hubs within a data processing system. Each one of the RIO hubs is assigned to one of multiple slave processors which are included within the data processing system. Each one of the slave processors which has an assigned RIO hub then configures its assigned RIO hub. Each RIO hub has an associated data structure that is updated with current configuration information by the slave processor assigned to configure that RIO hub. When the slave processor has finished configuring its assigned RIO hub, the slave processor then sets a configuration flag to indicate the completion of the configuration of the RIO hub.

Abstract: A field is defined in branch instructions which is interpreted by software as “Hint” bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified.

Abstract: A method, apparatus, and computer instructions for displaying data. Each entry in a plurality of entries for an overlay window attribute table (WAT) is set with identical information in which a window identifier is unnecessary for accessing the information in the overlay WAT. Information in a color WAT is retrieved using the set of window identifiers in response to receiving a set of window identifiers. The information in the overlay WAT is retrieved without requiring the window identifier. Pixels are displayed on a display screen using the information retrieved from the color WAT and the information retrieved from the overlay WAT.

Abstract: A sphere mode texture coordinate generator circuit for use in a graphics adapter of a data processing system is disclosed. The circuit includes a set of input multiplexers configured to receive x, y, and z components of a normal vector and a unit vector corresponding to the current vertex. The circuit further includes a set of functional units such as a floating point multiplier, a floating point adder, a floating point compare-to-zero unit, and an inverse square unit. The functional units are configured to receive outputs from the set of multiplexer and are enabled to perform floating point operations on the outputs of the set of multiplexers. A controller or state machine of the circuit is enabled to determine the state of select inputs to each of the set of multiplexers. The controller manages the multiplexer select inputs such that the circuit determines sphere mode texture coordinates in response to receiving the normal vector and the unit vector.

Abstract: A method, apparatus, and computer instructions for managing frames. Frames intended for isolation are identified in which the frames include in-use frames and free frames. Reservation of free frames from the frames identified as intended for isolation is requested. Successfully reserved frames are moved to an isolation list. In-use frames are marked, and unisolated/unmarked frames are identified. Any free frames in the unisolated frames are moved to the isolation list. In-use frames in the unisolated frames are marked and reservation of the in-use frames in the unisolated frames is released.

Abstract: A method and apparatus in a data processing system for processing a request to display a pattern. A plurality of partitions is created in a memory in a graphics adapter in the data processing system, wherein each partition within the plurality of partitions has a size equal to each of the other partitions within the plurality partitions. A determination is made as to whether the pattern is present within the plurality of partitions. The pattern is displayed using the plurality of partitions if the pattern is present within the plurality of partitions. The pattern is retrieved from another location if the pattern is absent from the plurality of partitions. Responsive to retrieving the pattern from another location, the pattern is stored if the pattern is within the size.

Abstract: A method, system and apparatus for cascading backup mirrors are provided. A mirroring map is created. The mirroring map includes at least three mirrors. A first mirror of the three mirrors is set to synchronize to a second mirror and a third mirror is set to synchronize to the first mirror. The first and the third mirror are backup mirrors and the second mirror is a working mirror. One of the backup mirrors is located remotely and the other locally.

Abstract: A system, method, and computer program product are disclosed for reducing overhead associated with software lock monitoring in a multiple-processor data processing system having a memory that is shared among the multiple processors. Multiple memory locations in the shared-memory are associated with one of multiple locks. Overhead is reduced by generating a trace hook only in response to activity associated with lock misses.

Abstract: A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system. The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system. The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions.