Abstract: A multi-chip apparatus is disclosed. In one form, the apparatus includes a carrier having a number of integrated circuit chips electrically coupled in a communications ring. The communications ring has carrier portions on the carrier and chip portions traversing the respective chips, permitting the communications ring carrier portions to be substantially straight, whereas at least one of the chip portions has a turn, enabling closure of the ring. In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.

Abstract: A system, method and computer program are provided for a virtual three-dimensional workspace wherein certain three-dimensional objects represent or serve as proxies for a variety of user interactive application programs. Such objects may be selected or triggered by the user to bring forth planar two-dimensional interactive user interfaces having images resembling those of their respective representative 3D objects so that a user may intuitively note the resemblance and select the appropriate object to result in the planar two-dimensional interactive interface appearing in front of the three-dimensional workspace. This two-dimensional planar interface remains active and unaffected by changes to its representative three-dimensional object during the course of navigation or otherwise.

Abstract: A method and apparatus in a graphics system. The graphics system includes an input, wherein the input receives graphics data, wherein the graphics data includes position coordinates and a depth coordinate for an object. An output is present in which the output transmits processed graphics data. The graphics system also contains a plurality of processing elements, wherein the plurality of processing elements generates the processed graphics data. A first processing element within the plurality of processing elements is connected to the input and a last processing element within the plurality of processing elements is connected to the output. A selected processing element within the plurality of processing element receives the position coordinates and the depth coordinate, inverts the depth coordinate to form an inverted depth coordinate, and multiplies the position coordinates by the inverted depth coordinate.

Abstract: A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.

Abstract: A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.

Abstract: A method, system and program for architecturally identifying data processor implementations are provided. The invention comprises assigning a plurality of least significant bits in a processor's identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.

Abstract: A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller.

Abstract: Described is a method for isolating faults to a correct field replaceable unit (FRU) of a data processing system. When a processor timeout occurs, a fault isolation logic is triggered and checks the boot record to determine if the timeout occurred because of an FRU fault before or after the service processor completed its system initialization. When the timeout occurred because of fault that occurred while the service processor was loading operating system (OS) (e.g., AIX) instructions from the boot device in the input/output (I/O) subsystem, then the FRU callout indicates a boot fault associated with the I/O planar and the CPU (processor) card. When the FRU fault occurred prior to fetching the OS instructions from the boot device or after the service processor completed its system initialization procedures, then the FRU callout is attributed to the processor card and backplane. Attributing boot error faults to incorrect FRUs is therefore substantially eliminated.

Abstract: A modified system causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64# signal low. This will synchronize reset and REQ64#, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.

Abstract: The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual copy of the I/O facilities to be shared. The remote translation control entry table on the hosted partition is loaded with data from a hypervisor in response to requests made by the OS running in the hosted partition. The hypervisor, in response to requests from the OS running in the hosting partition, copies the data from the remote translation control entry into a standard translation control entry table on the hosting partition owning the physical I/O facilities that target the I/O page buffers of the hosted partition to perform the desired I/O operation. The I/O page buffers of the hosted partition are accessed by the hosting partition's I/O facilities using the data stored in the standard translation control entry table.

Abstract: An apparatus, system and method for booting a data processing system from a removable medium is provided. With the apparatus, system and method, a boot sequence is started to a point at which a file system is available. At that time, driver files and registry information is copied from the data processing system to the removable medium. The boot sequence is then restarted using the driver files and registry information copied. In this way, a removable medium, having application data and user defined setting information, may be used to customize a plurality of different data processing systems while still providing the user access to the particular data processing system configuration and peripheral devices of the data processing system. Thus, the user's customized settings provide a system interface that is familiar to the user while being able to make use of different hardware devices.

Abstract: A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus.

Abstract: A data processing system and method are disclosed for displaying a graphical depiction of the system configuration of the data processing system. Execution of a boot process of the data processing system is started. Prior to a completion of the boot process, a configuration of the data processing system is determined by the system itself. A graphical depiction of the configuration is then generated. The graphical depiction is then graphically displayed utilizing a display screen which is included in the data processing system. The graphical depiction illustrates each device included in the system as well as how the devices are interconnected. Thereafter, the execution of the boot process is completed. The steps of determining a configuration, generating a graphical depiction, and graphically displaying the graphical depiction are completed prior to completing the booting the data processing system, and thus prior to an operating system being executed by the data processing system.

Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.

Abstract: A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus.

Abstract: A debug card suitable for use with a data processing system is disclosed. The card includes a microcontroller, a storage device connected to the microcontroller; and, connected to the microcontroller, means for tapping into a communication bus of the data processing system where the bus communicates information between a processor of the data processing system and a display panel. The microcontroller is configured to record the information received by the display panel from the processor in the storage device when the debug card is connected to the communication bus. In one embodiment, the communication bus and the microcontroller are I2C compliant. In this embodiment, the debug card may have its own I2C address thereby enabling the debug card to communicate with the processor. The debug card may further include a serial port connected to the microcontroller. The serial port enables downloading the information stored in the storage device to an external computer.

Abstract: A method and apparatus in a data processing system for updating a buffer containing display information used to display pixels from a first layer and a second layer on a display in the data processing system. Pixels from the first layer and pixels from the second layer are identified in a transparent region. The display information is updated in the buffer for pixels in the first layer in the transparent region. Correct display information is assigned to pixels in the second layer in the transparent region.

Abstract: A business method for identifying business competitors' customers through Web searches of job listing databases or job boards and company Web sites where jobs are also often posted directly. Items such as competitors' business names, product names, acronyms, etc., are used as keywords and the search engine results provide an index of potential customers who are posting job listings for employees skilled in competitive products. Once the Web sites and/or Web pages posting job listings of these potential customers are located, additional information relative to doing business with said potential customers may be extracted from such pages and Web sites through “spider” or “Web crawler” routines.

Abstract: A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter. If the number of input interrupt lines is greater than the number of output lines, then interrupt sharing is necessary. The number of input interrupt lines can be determined automatically by scanning all the card slots or can be determined by values stored in lookup tables. The algorithm to determine a logical mapping of the input interrupt lines to the output lines, in cases where interrupt sharing is required, can be based on a number of factors. A simple approach is to distribute the interrupts as equally as possible. Another algorithm may take into account the expected frequency of interrupts based on the device involved. Yet another approach may use a set of predetermined priorities. Since these algorithms are implemented in firmware or software, they can be changed to meet a particular set of needs.