Abstract: In a system where a path history vector is used in conjunction with a branch history table, an algorithm is disclosed for reducing the number of bits required for a path history vector. The path history vector is used to address a branch history table. Since the path history vector may contain a large number of zeros, this may lead to branch predictions that are inaccurate because of the limited size of the path history vector and the corresponding branch history table. A compression algorithm is disclosed where zeros in the path history vector are compressed. The number of zeros greater than one but less than a maximum are compressed in a single zero. With a compressed path history vector, inner loops with larger iterations or loops with larger instructions or branches are predicable with greater accuracy.

Abstract: A method, system and computer readable instructions for generating a random number consisting of a plurality of binary bits is provided. A race condition gate is set. An atomic lock is accessed wherein a first racer representing a first binary bit and a second racer representing a second binary bit race toward the atomic lock upon release of the race condition gate. A determination is made as to which of the first racer, representing the first binary bit, and the second racer, representing the second binary bit, gain access to the atomic lock earliest. The atomic lock is retrieved based on the determination of which racer gains access to the atomic lock earliest. A single binary value is then written to a data stream, the single binary value is based on which of the first racer and the second racer retrieves the atomic lock.

Abstract: A method and apparatus for pausing a send queue while preventing sympathy error from propagating through a SAN fabric system is provided. The method and apparatus place a send work queue in an error state, i.e. pauses the send work queue, when a reliable data error occurs in the send work queue but does not place any other work queues in an error state. In this way, the send queue experiencing the error is not able to send any further messages until error recovery is performed. However, other work queues continue to be able to send and/or receive messages. Once error recovery is performed, the send work queue that was placed in the error state is returned to a working state and is able to continue to send messages. In addition, the send queue that was in the error state will send the messages that it attempted to send at the time of the error. The messages sent will continue from a last known point at which the send work queue was operating properly.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.

Abstract: An apparatus and method for providing selective views of on-line surveys are provided. With the apparatus and method, each survey has a survey data structure and a template data structure. In a preferred embodiment, the data structures represent tree structures having nodes, child nodes, links between nodes and child nodes, and the like, for the survey and the template. Changes to the survey are made in the template data structure. The survey data structure and the template data structure are compared to one another, and nodes are either added, subtracted, or modified based on the differences between the survey data structure and the template data structure. In this way, the survey data structure retains the information that is already in present in it, such as the questions and answers previously provided. Thereafter, when the survey is again presented to a user, the user's previous answers to questions still remaining in the survey are displayed but no answers are displayed for newly added questions.

Abstract: A system and method for accessing a cache memory having a redundant array without displacing a cache line in a main array are described. Redundant rows of a cache memory array are used as extra cache lines for the cache memory array. Operations can be performed on these extra cache lines without effecting previous cache line values which have been brought into the cache memory array. These extra cache lines thus provide for temporary cache storage without causing a cache line reloaded into the cache memory array. This selective access of memory without disturbing the current contents of the cache memory array increases system throughput by minimizing the number of times that a cache memory might have to be reloaded.

Abstract: A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and maintaining security over the distribution mechanism. In one embodiment, this invention is used by a data processing system including a system processor connected to a plurality of operating system instances that are allocated individual system functions. Using logical partitioning, each operating system instance's access is limited to its own partition. Address buses to system functions are manipulated to make the functions appear at appropriate memory locations expected by the operating system instances. Accordingly, an inverter can be inserted on the address bus to change the address to a given distance in memory safe from operating system accessibility, for example, a page boundary.

Abstract: The present invention is a mechanism for providing redundancy in the register file of a microprocessor such that registers having a defective operational status, as determined by testing, can be tolerated and the baseline specification of the microprocessor can be met. The present invention utilizes the register renaming capability of a microprocessor to allow additional registers, above those called for in the specification to be provided. The registers are then tested and those found “bad” are identified and avoided by the allocation/deallocation logic, which is used to assign registers to the various instructions being executed by the microprocessor. More particularly, the present invention maintains a list of physical registers in a register file that have a functional operational status and are available to be allocated to various instructions as they execute. The allocated registers are typically used to store interim data resulting from the execution of the assigned instruction.

Abstract: A method for managing allocation of network resources within the distributed computer system is provided. Specifically, the network traversal time and the end node response time for requests and/or packets being routed in a switch-connected system area network are utilized to determine the total round trip time for completion of the particular network operation. The sum of the timeout values for all switches that participate in routing the request from a requester (source) to the receptor node (target) is provided to the requester's channel adapter (CA). The time-out values are provided by the switch manufacturer and are sent to a network Subnet Manager (SM) via SM packets (SMP). The timeout values added together represent the SubnetTimeout. The time-out value of the target channel adapter (CA), the ResponseTime, is also provided to the requester. The requester then utilizes one of two timeout equations to calculate the overall response time required for the request to be completed.

Abstract: Smoother transitions between changing cursor images which are less stressful to the interactive user of a computer controlled display are provided by apparatus for changing the cursor image, including a frame buffer for storing the display screen image as a pixel array, a separate display buffer for storing the current cursor image as a pixel array, together with apparatus for storing an alternate cursor image as a pixel array during the display of the current cursor image, and means for replacing the current cursor image with the alternate cursor image. In raster scan apparatus for maintaining screen images in the frame buffer on said display screen, there are means for effecting the replacement of said cursor images during a vertical blanking period in said raster scanning.

Abstract: A method and apparatus preserve the data structures established in the earliest stage of initial power load, rather than each system firmware component rediscovering the hardware components of the system. Thus, the data structure is available at later stages for other firmware components. In a logical partitioning machine, the open firmware partition manager can utilize the data structure to support the partition's open firmware device tree construction. The partition manager customizes the copies of these data structures residing in the partition's memory. For hardware devices in the system but not belonging to the partition, the device information is cleared and marked invalid. After the data structures are established and updated by the earliest firmware I/O configuration component, the addresses of these structures are provided to the open firmware component. The open firmware copies these data structures to its internally safe working area and uses the copies for its normal operation.

Abstract: A system and method for recovering a global history vector is implemented. In deeply pipelined central processing unit (CPU) architecture instruction fetches may precede execution by several processor cycles. A global history vector (GHV) may be used in predicting the branches in a current fetch cycle. Fetch redirection events, such as a cache miss, or a branch misprediction may lead to loss of synchronization of instruction fetches and the GHV. To recover the GHV following a redirection event, registers are provided to hold a GHV being used to predict branches in a current fetch cycle and two subsequent GHVs. On the occurrence of a redirection event, a fetch redirection is generated. GHV update logic detects the fetch redirection and resets the current GHV to a selected one of the stored values.

Abstract: A method for detecting head-to-disk interference events in a disk drive is provided. The invention comprises coupling a transducer to an air filter in the disk drive, wherein the transducer detects changes in magnetic readings due to debris produced by physical contact between a read/write head and a magnetic storage medium (head crash). The recirculation filter is monitored during disk drive operations and comparing magnetic readings from the transducer with defined parameters. If the transducer readings exceed the defined parameters, the spindle motor of the disk drive is shut off, thus stopping the rotation of the disk and minimizing data loss and damage due to the head crash.

Abstract: A method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I2C) buses are provided. Upon resetting a I2C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device's address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.

Abstract: A data processing system, method, and computer program product for automatically tracking insertions of integrated circuit devices into receptacle devices. An insertion of an integrated circuit device is automatically detected utilizing the data processing system. An insertion count that is associated with the integrated circuit device is automatically incremented in response to a detection of an insertion of the integrated circuit device. The insertion count is used to track insertions of the integrated circuit device.

Abstract: An apparatus and method for performing surveillance prior to boot-up of an operating system is provided. The apparatus and method include an error detector that monitors a boot-up sequence of a support system for the occurrence of an error. If an error is detected, a unit check signal is output by the error detector. The unit check signal is received by either the support system or an error message output device and a corresponding error message is generated and output for use by a user of the computing system.

Abstract: A method of de-allocating multiple processor cores sharing a failing bank of memory is disclosed. The method allows new multiple-processor integrated circuits with on-chip shared memory to be de-allocated using existing technology designed for use with single-processor integrated circuit technology.

Abstract: A method, system, and apparatus for reestablishing communications between a host and a service processor after the service processor has ceased to function correctly is provided. In one embodiment, the host exchanges heartbeat signals with the service processor. The heartbeat signals indicate that the service processor is active and functioning. In response to a failure to receive a heartbeat signal or in response to some other indication that the service processor is not performing correctly, the host causes a hard reset of the service processor. In addition, the service processor can detect a failure within itself and initiate a hard reset to itself. After the hard reset, the service processor returns to a monitoring mode without performing initial tests of the data processing system. Furthermore, the data processing system remains active and is not shut down during the hard reset of the service processor.

Abstract: A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.