Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths.

Abstract: A number of structural modules are configured to be secured together and to be secured to a foundation. Each of the structural modules is without one or more sidewalls, such that when the structural modules are secured together they form a building structure that encloses an open region which continuously extends through interiors of the structural modules. Each of the number of structural modules is structurally formed to be independently transported. A power module is configured to be secured to one of the structural modules and to the foundation. The power module is defined as an enclosed structure and is structurally formed to be independently transported. The power module is equipped with electrical components for supplying and distributing electrical power to a pre-defined layout of data equipment to be deployed within the open region of the building structure formed by the number of structural modules.

Abstract: A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.

Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.

Abstract: Data-mining software initializes a loop by (a) assigning the messages in an online discussion on a website to a single logical cluster that is one of a group of logical clusters and (b) determining a measure of similarity-adjusted entropy for the group of logical clusters. Then the data-mining software randomly reassigns one of the messages to another logical cluster that is randomly selected from the group of logical clusters and again determines a measure of the similarity-adjusted entropy for the group of logical clusters. If the subsequent measure of similarity-adjusted entropy is greater than or equal to the earlier measure of similarity-adjusted entropy, the data-mining software undoes the reassignment. If the subsequent measure of similarity-adjusted entropy is less than the earlier measure of similarity-adjusted entropy, the data-mining software replaces the earlier measure with the subsequent measure. The data-mining software repeats the operations of the loop until convergence is reached.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the diffusion level layout to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A number of PMOS transistor devices is equal to a number of NMOS transistor devices in the restricted layout region. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A method for detecting plasma unconfinement in a reaction chamber during a bevel edge cleaning operation is provided. The method initiates with selecting a wavelength associated with expected by products of a bevel edge clean process. The method includes cleaning the bevel edge area of a substrate and monitoring the intensity of the selected wavelengths during the cleaning for deviation from a threshold wavelength intensity. The cleaning is terminated if the deviation from the threshold wavelength intensity exceeds a target deviation.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: The present invention is a method, computer-readable medium and an apparatus for protection and recovery of non-redundant computer-readable information stored in a memory having multiple segments that features replacing computer-readable information stored in one of the multiple segments based upon a determination that computer-readable information stored in one of the remaining segments of the multiples segments is in a desired state. To that end, the memory device operates synergistically with a shelf manager, which maintains a state of computer-readable information in the differing address ranges of the memory device, so that any computer-readable information replaced in memory device may be achieved by executing uncorrupted computer-readable information stored in the memory device.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: Methods and system for managing demand for an object includes capturing information about the object through a mobile device associated with a user. The mobile device is configured to capture information about the object that include one or more of a spatial, temporal, topical and social attributes of the object. The identity of the object is verified and validated using this metadata captured by the user through the device from the real world object or its proxy. Upon successful verification and validation, the object and its metadata are automatically added to a wish list of the user. An aggregate list is generated using the attributes and metadata of the object from a plurality of users. The aggregate list defines a source of demand for the object. The object is tracked as it progresses through various phases of ownership cycle using dynamic demand calculations based on the information associated with the objects, the users and the aggregate lists.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.

Abstract: Porous organic-inorganic hybrid materials with crystallinity and a method for preparing the same are provided. The method comprises preparing a reaction solution containing a mixture of at least one inorganic metal precursor, at least one organic compound which may act as a ligand, and a solvent (step 1); and forming porous organic-inorganic hybrid materials with crystallinity by reacting the reaction solution (step 2), wherein the reaction is carried out under the pressure of about 3 atm or less.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In one example, a chamber for wafer bevel edge cleaning is provided. The chamber includes a bottom electrode having a bottom electrode surface for supporting the wafer when present. Also included is a top edge electrode surrounding an insulating plate. The insulator plate is opposing the bottom electrode. The top edge electrode is electrically grounded and has a down-facing L shape. Further included in the chamber is a bottom edge electrode that is electrically grounded and spaced apart from the bottom electrode. The bottom edge electrode is disposed to encircle the bottom electrode. The bottom edge electrode is oriented to oppose the down-facing L shape of the top edge electrode.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.