Patents Represented by Attorney, Agent or Law Firm Martine Penilla & Kim, LLP
  • Patent number: 6267545
    Abstract: An interlocked control system is provided for dual sided slot valves contained in a vacuum body between each of a plurality of adjacent process and transport modules. Separate valves are provided for each of two valve body slots, one body slot being separately closed or opened independently of the other. The separate valves allow a vacuum in the transport module while an adjacent process module is open to the atmosphere for servicing. Under control of the system, the valve may allow separate operation of the transport module and certain ones of the process modules, while a selected one of the process modules is in either a maintenance state or a locked out state for servicing. The system includes a separate controller for the transport module and a separate controllers for the process modules. A control interface coordinates the flow of signals between the controllers and local devices, and system user interfaces provide inputs to the control system from operational and service personnel.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 31, 2001
    Assignee: Lam Research Corporation
    Inventors: Benjamin W. Mooring, Nicolas J. Bright
  • Patent number: 6267642
    Abstract: In a machine for planarizing wafers, when a spindle carrier descends over the load station, it needs a way of determining whether it should descend to a first position suitable for depositing a wafer onto the load station or whether it should descend to a lower second position suitable for acquiring a wafer that is already present on the load station. The present invention provides a way of making this determination. The load station includes three upwardly-directed nozzles for use in supporting a wafer on three separate spaced cushions of purified water. The nozzles are supplied through branch conduits from a supply main. When no wafer is present, the pressurized water meets with little resistance as it is discharged from the nozzles. Accordingly, the pressure in the branches is relatively low. In contrast, when a wafer is present the wafer partially impedes the discharge of the water from the nozzles, causing the pressure in the branches to be greater than when no wafer is present.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: July 31, 2001
    Assignee: Lam Research Corporation
    Inventors: Michael R. Vogtmann, Terry L. Lentz
  • Patent number: 6251722
    Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: June 26, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Houng-chi Wei, Tso-chun Tony Wang
  • Patent number: 6251770
    Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: June 26, 2001
    Assignees: Lam Research Corp., Novellus Systems, Inc.
    Inventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
  • Patent number: 6247197
    Abstract: A brush assembly includes a distributor having a slot matrix formed in an outer surface of the distributor, the slot matrix including a plurality of longitudinal slots intersecting a plurality of annular slots. The brush assembly further includes a housing having an inner surface abutting the outer surface of the distributor, a brush mounted on the housing and a shaft. During use, the flow of liquid from the shaft to the housing flows through the longitudinal slots and annular slots of the distributor. By appropriately selecting the dimensions and numbers of these slots, the flow of liquid from the shaft to the housing is readily redistributed. For example, the flow of liquid is redistributed to provide a greater amount of liquid to the ends of the brush than to the center of the brush.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: June 19, 2001
    Assignee: Lam Research Corporation
    Inventors: Jim Vail, Mike Wallis
  • Patent number: 6244811
    Abstract: A load lock wafer transfer face is provided at an acute angle with respect to a footprint dimension line, so the length of the footprint dimension line does not include the entire minimum length of the wafer transfer distance that must separate a robot from the wafer transfer face of a load lock. Two adjacent load locks provided for use with a robot have two load lock wafer transfer faces defining a nest, in that each such face is at an acute angle with respect to the footprint dimension line. A robot is mounted for rotation at a fixed location relative to wafer cassettes and to the nested load lock wafer transfer faces, avoiding use of a robot track to move transversely. Because the faces are at the acute angle, there is only a component of, and not the entire, minimum wafer transfer distance extending in the direction of the footprint dimension line.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: June 12, 2001
    Assignee: Lam Research Corporation
    Inventors: Tony R. Kroeker, Larry Cook
  • Patent number: 6246116
    Abstract: A buried wiring line. The structure of the buried wiring line at least comprises a conductive doped region in a provided substrate and a silicon nitride region formed around the conductive doped region in the substrate. The silicon nitride region, which comprises a first silicon nitride below the doped region and a second silicon nitride layer beside the doped region, isolates the buried wiring line from the substrate.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Tien-Jui Liu
  • Patent number: 6245625
    Abstract: A method of fabricating a self-aligned contact window structure is described in which a substrate is provided with a plurality of gates formed on the substrate and a plurality of lightly doped regions is formed in the substrate on both sides of the gate. A first dielectric layer of a certain thickness is then formed on the substrate with the surface of the first dielectric layer being lower than the surfaces of the gates such that the sidewalls of the gates are partially exposed. A plurality of spacers is further formed on the exposed sidewalls of the gates. Using the gates and the spacers as masks, the first dielectric layer is anisotropically etched until the lightly doped regions are partially exposed. Using the gate and the spacer as masks, a plurality of heavily doped regions is formed in the lightly doped region and in the substrate. A second dielectric layer is formed covering the gates. The second dielectric is then defined to form a self-aligned contact window.
    Type: Grant
    Filed: June 19, 1999
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Patent number: 6242044
    Abstract: Disclosed is method and apparatus for distributing a chemical over the surface of a substrate. The method includes depositing the chemical on a portion of the surface of a substrate near the center of the substrate. The method further includes controlling the temperature of the surface of a substrate so that the viscosity of the chemical is calibrated to cause the chemical to be deposited on the surface of the substrate in a substantially uniform manner.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: June 5, 2001
    Assignee: Fairchild Technologies USA, Inc.
    Inventor: Andreas Ebert
  • Patent number: 6242360
    Abstract: The present invention provides a plasma processing apparatus, system, and method for providing RF power to a plasma processing chamber. The plasma processing system includes an RF generator, a plasma chamber, a match network box, a first cable, a second cable, and means for electrically isolating the match network box. The RF generator is generates RF power for transmission to the plasma chamber. The plasma chamber receives the RF power for processing the wafer and is characterized by an internal impedance during the plasma processing. The plasma chamber has one or more walls for returning RF currents. The match network box is capable of receiving the RF currents and generates an impedance that matches the internal impedance of the plasma chamber to the impedance of the RF generator. The first cable is coupled between the RF generator and the match network box for transmitting RF power between the RF generator and the match network box.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: June 5, 2001
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Babak Kadkhodayan, Andras Kuthi
  • Patent number: 6240588
    Abstract: A brush core and the method for making a brush core for use in substrate scrubbing are provided. The substrate can be any substrate that may need to undergo a scrubbing operation to complete a cleaning operation, etching operation, or other preparation. For instance, the substrate can be a semiconductor wafer, a disk, or any other type of work piece that will benefit from a brush core that can deliver uniform controlled amounts of fluid through the brush along an entire length of the brush core. The brush core is defined by a tubular core having a length that extends between a first end and a second end. The first end has an opening into a bore that is defined through a middle of the tubular core and extends along an inner length of the tubular core. A first plurality of holes are oriented along a plurality of first lines that extend in the direction of the length of the tubular core, and each of the first plurality of holes define paths to the bore of the tubular core.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: June 5, 2001
    Assignee: Lam Research Corporation
    Inventors: Tanlin Dickey, Julia S. Svirchevski, Donald E. Anderson, Mike Ravkin, Helmuth W. Treichel, Roy Winston Pascal, Douglas S. Gardner
  • Patent number: 6240527
    Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: May 29, 2001
    Assignee: Roxio, Inc.
    Inventors: Eric Schneider, Chuck Ferril, Doug Wheeler, Larry Schwartz, Edward Bruggeman
  • Patent number: 6239472
    Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: May 29, 2001
    Assignee: Philips Electronics North America Corp.
    Inventor: Jayarama N. Shenoy
  • Patent number: 6240475
    Abstract: According to the present invention, a function timer is started whenever the PCI bus is granted to the function that did not access the PCI bus prior to the last bus idle state. The timer counts down to zero and waits until another function requests the PCI bus. During the time the timer is not zero, the current function will have the highest priority. Even if a PCI bus disconnect signal or retry signal forces the current function to deassert the request signal and start the request again, the current function is guaranteed to win the arbitration among the multiple contenders within the multi-function device. Since during the time slot, the same function will the granted access to the PCI bus, the next request will most likely be readily available from the PCI bridge's buffer which has additional data stored in anticipation for the next request. The use of the PCI bridge's buffer will maximize the system memory bus usage while increasing the PCI bus throughput.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: May 29, 2001
    Assignee: Adaptec, Inc.
    Inventor: Surendra Anubolu
  • Patent number: 6236073
    Abstract: An electrostatic discharge protective circuit formed on a substrate is described. A gate electrode is formed over the substrate. A drain region is formed in the substrate at one side of the gate electrode. A source region is formed in the substrate at the other side of the gate electrode. A dielectric layer having a drain contact and a source contact formed therein is formed over the substrate, wherein the drain contact is electrically coupled to the drain region and the source contact is electrically coupled to the source region. A plurality of floating polysilicons is formed on the substrate in the dielectric layer between the drain contact and the gate electrode. Since the floating polysilicons are staggered on the substrate in a checkered pattern, the electrostatic discharge transient current path is greatly increased. Therefore, the electricity dissipation length is greatly increased. Hence, the protective efficacy of the electrostatic discharge protective circuit can be improved.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: May 22, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Chen-Chung Hsu
  • Patent number: 6236222
    Abstract: Disclosed is a method for inspecting electrical interconnections in a multi-level semiconductor device. The method includes forming an interconnect structure in the multi-level semiconductor device. The interconnect structure has a lower metallization layer that lies in a lower level and an upper metallization layer that lies in an upper level. The method includes performing a passive voltage contrast operation using a scanning electron microscope to produce an image of the upper metallization layer of the interconnect structure. The method further includes inspecting the image produced by the scanning electron microscope to determine whether a misalignment is present in the interconnect structure. Additionally, the scanning electron microscope applies a beam of electrons over a selected portion of the interconnect structure, and secondary electrons are emitted off of the upper metallization layer in response to the beam of electrons.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: May 22, 2001
    Assignee: Philips Electronics North America Corp.
    Inventors: Harlan Sur, Jr., Ian R. Harvey
  • Patent number: 6235647
    Abstract: A deposition process for forming a void-free dielectric layer is described. A first dielectric layer 204 is formed over a conductor pattern 202. A second dielectric layer 206 is formed to conform to the first dielectric layer. A third dielectric layer 208 is formed to cover the second dielectric layer. The first, second, and third dielectric layers can be formed by high density plasma deposition, atmospheric pressure deposition, and plasma enhanced deposition, respectively. The second dielectric layer can alternatively be formed by plasma enhanced deposition.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: May 22, 2001
    Assignee: United Microelectronics Corp.
    Inventors: I. T. Chen, Horng-Bor Lu
  • Patent number: 6230753
    Abstract: A method and apparatus for cleaning a wafer oriented vertically is provided. The apparatus includes a first brush and a second brush located horizontally from the first brush. During unloading of the wafer after cleaning, the wafer is located vertically between the first and second brushes and on a pair of rollers. A finger tip located vertically above the region between the first and second brushes contacts an edge of the wafer and thus hold the wafer in the precise unloading position at which a wafer transfer robotic arm has been programmed to engage/disengage the wafer. Accordingly, the wafer is reliably and repeatedly engaged by the robotic arm.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: May 15, 2001
    Assignee: Lam Research Corporation
    Inventors: Oliver David Jones, Jim Vail
  • Patent number: 6233282
    Abstract: The present invention teaches a variety of methods and apparatus for providing reduced bit rate digital video formats. Generally speaking, the present invention decodes digital video data stored in a first, higher bit rate format and then encodes the digital video data into a second fixed bit rate digital video format that is less than the first fixed bit rate digital video format. Several different compression techniques are contemplated. For example, in one embodiment the dc and header information is preserved intact, higher ac frequency information is deleted, and new macroblocks are created for the decoded video segments. The new macroblocks are then assembled into shorter length video segments. Another technique involves quantizing the DC and AC frequency information. Of course, both the high frequency “lopping” and the quantizing techniques can be combined for even further compression.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: May 15, 2001
    Assignee: Adaptec, Inc.
    Inventor: Enzo Guerrera
  • Patent number: 6229685
    Abstract: A capacitor and a method of making the capacitor is provided. The capacitor includes a metallization line with a high dielectric constant layer defined over the metallization line. A thin metallization film is defined over the high dielectric constant layer, such that the thin metallization film defines a top plate of the capacitor, the high dielectric constant layer defines a dielectric for the capacitor, and the metallization line defines a bottom plate for the capacitor. The metallization line is defined from a metallization level and the thin metallization film is defined before a next metallization level above the metallization level is defined.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 8, 2001
    Assignee: Philips Electronics North America Corp.
    Inventors: Subhas Bothra, Dipankar Pramanik, Calvin T. Gabriel