Patents Represented by Attorney, Agent or Law Firm Martine Penilla & Kim, LLP
  • Patent number: 6229812
    Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: May 8, 2001
    Assignee: Paxonet Communications, Inc.
    Inventors: Bidyut Parruck, Chetan V. Sanghvi, Vinay Kumar Bhasin, Makarand Dharmapurikar, Uday Govind Joshi
  • Patent number: 6226241
    Abstract: An improved file system and method for incrementally recording data on compact discs is disclosed. The improved file system and method employs compact discs physically formatted in accordance with the so-called Orange Book specification. Files to be stored are selected from time to time and are divided into packets. The packets are then recorded in a program area of the compact disc together with link, run-in and run-out blocks in a format compatible with the Orange Book rules for linking incrementally recorded packets. File linking information is also stored with each file. If desired, files may, but need not, be recorded in a form compatible with existing CD-ROM and drivers adhering to the ISO-9660 standard. As selected files are recorded, file and directory information are stored in a first storage area either in a host system or in a track of the compact disc in a double linked and highly efficient format.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: May 1, 2001
    Assignee: Roxio, Inc.
    Inventors: Andrea D'Amato, Fabrizio Caffarelli
  • Patent number: 6226782
    Abstract: Disclosed is an apparatus for generating mask data suitable to produce a support pillar mask used in air dielectric interconnect structures. The apparatus includes a mask data scanner configured to select features having an interconnect dimension from a first mask. The features having the interconnect dimension being defined to electrically interconnect devices distributed on a substrate. The apparatus further includes a mask data comparing engine for comparing mask data associated with an intermediate support pattern and mask data associated with the features having the interconnect dimension selected by the mask data scanner. The comparing being configured to identify a mask area where the intermediate support pattern and the features having the interconnect dimension overlap. Preferably, the identified mask area defines the location of a plurality of pillars.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: May 1, 2001
    Assignee: Philips Electronics North America Corp.
    Inventors: Edward D. Nowak, Subhas Bothra
  • Patent number: 6222388
    Abstract: The first pulse problem for a low-voltage differential SCSI bus driver is remedied by supplying greater power for a first pulse of a bus line after a steady state condition. Activity detection circuitry detects when a signal has remained in a steady state for a number of bus cycles and enables an additional power boosting differential driver to deliver an appropriate amount of power for a limited amount of time in order to produce a quality first pulse while minimizing power output. The extra power needed to remedy the quality of the first pulse is only supplied for the duration of the first pulse so that the output driver strength is minimized and the total power over time that an integrated circuit must dissipate is reduced. In another embodiment, instead of greater than normal power being delivered for a first pulse, the output driver is decreased in its output drive strength while an output remains in a particular state.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: April 24, 2001
    Assignee: Adaptec, Inc.
    Inventor: Walter Francis Bridgewater, Jr.
  • Patent number: 6222791
    Abstract: The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: April 24, 2001
    Assignee: Artisan Components, Inc.
    Inventors: Scott T. Becker, Venkata N. Rao
  • Patent number: 6221759
    Abstract: Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming an etch stop layer over the oxide layer and forming a set of adjacent trenches in the oxide layer through a portion of the etch stop layer. The method also includes forming a resist layer at least partially over the etch stop layer. The resist layer is formed in a via pattern to expose the set of adjacent trenches through the via pattern. The method further includes etching the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose at least a portion of the first metal layer so as to form a via under each of the adjacent trenches.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: April 24, 2001
    Assignee: Philips Electronics North America Corp.
    Inventors: Subhas Bothra, Stephen L. Skala
  • Patent number: 6216328
    Abstract: Disclosed is a transport chamber and a method of making a transport chamber having a robot arm installed within the transport chamber. The robot arm may be implemented to retrieve a substrate from at least one storage facility that is external to the transport chamber, and insert the substrate into at least one processing chamber that is external to the transport chamber.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: April 17, 2001
    Assignee: Lam Research Corporation
    Inventors: Trace L. Boyd, Eric A. Terbeek
  • Patent number: 6218261
    Abstract: A method of fabricating a bottom electrode is provided. A dielectric layer comprising a first opening is formed on the substrate. A conductive layer is formed on the dielectric layer to fill the first opening. A first patterned mask layer comprising a second opening is formed on the conductive layer. An isotropic etching step is performed on the conductive layer with the first patterned mask layer serving as a mask. A recess with a non-vertical sidewall is formed on the conductive layer under the second opening. The first patterned mask layer is removed. The conductive layer is patterned to form a bottom electrode with the recess. A hemispherical grained silicon layer is formed on the bottom electrode.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: April 17, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Yi-Tyng Wu
  • Patent number: 6213136
    Abstract: In a spin dryer for semiconductor wafers, the wafer is held beneath a platen with its active side (i.e., the side containing the components or circuitry) facing upward. One or more nozzles spray rinse water on the top surface of the wafer and the wafer is rotated to remove the excess rinse water, thereby drying the wafer. A splash guard adjacent the edge of the wafer insures that the excess rinse water thrown off by the spinning wafer is deflected downward where it cannot again come into contact with the active side of the wafer. The platen is rotated dry at the same time, with no rinse water being splashed back onto the active side of the wafer. The spin dryer also includes a separate section which cleans and dries the end-effector of the robot which inserts the wafer into the spin dryer while the wafer is being dried.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: April 10, 2001
    Assignee: Lam Research Corporation
    Inventor: Oliver David Jones
  • Patent number: 6211068
    Abstract: A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that expose a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned, and the photoresist material inside the opening is turned into a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: April 3, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Yimin Huang
  • Patent number: 6212656
    Abstract: A method of configuring scan mode circuitry of an integrated circuit (IC) device includes parsing through an initial file of the scan-flops that are to be included in the scan mode circuitry. The initial file can be prepared with a synthesis tool such as Synopsys. A particular subset of scan-flops are parsed, according to an identified number to be included in each scan chain. A holding tank is created to hold each subset of scan-flops for each scan chain. Each holding tank is then used to form a scan path and to stitch the corresponding scan chain. The parsing of the scan-flops into holding tanks can be performed with a c-shell script. Also, the c-shell script can be called by a Synopsys dc_shell script.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: April 3, 2001
    Assignee: Adaptec, Inc.
    Inventors: Brian Thomas Fosco, Bruce Pember
  • Patent number: 6207567
    Abstract: A method of fabricating a glue layer and a barrier layer. A Ti layer is formed with a collimator sputtering in the via opening or the contact opening of the substrate. Through the control of flow of N2 and Ar, a nitride mode TiNx layer is formed on the Ti layer by sputtering. The nitride mode TiNx layer and the Ti layer uncovered by the nitride mode TiNx layer are treated with N2 RF plasma. This strengthens the structure of the nitride mode TiNx layer and allows the reaction with the exposed Ti layer so that it is transformed into a TiNx layer.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: March 27, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chein-Cheng Wang, Shih-Chanh Chang
  • Patent number: 6207556
    Abstract: A method for fabricating a metal interconnect involves forming a first dielectric layer on the substrate having metal lines formed thereon, wherein the top surface of the first dielectric layer is lower than that of the metal line. As a result, the top surface and a part of the sidewall of the metal line are exposed. A spacer is then formed on the exposed sidewall of the metal line. A second dielectric layer is formed on the substrate, wherein the spacer has different etching selectivity from the second dielectric layer. With the spacer serving as an etching stop layer, a via opening is formed in the second dielectric layer, while the via opening is filled with a metal plug to form a via plug.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: March 27, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Shih-Ying Hsu
  • Patent number: 6204980
    Abstract: An integrated circuit servo system demodulator that incorporates a high speed gain stage with DC offset cancellation. The gain stage receives a differential voltage signal representing a servo burst and converts the differential voltage signal to a differential current signal by a transconductance amplifier. The differential current signal is full-wave current rectified and converted to a full-wave rectified voltage signal by a transimpedance amplifier. A DC offset cancellation circuit is coupled between the full-wave current rectifier and transimpedance amplifier and functions to mirror and subtract, from the rectified current signal directed to the transimpedance amplifier, any DC leakage current developed by the rectifier which would generate a DC offset voltage through the transimpedance amplifier.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: March 20, 2001
    Assignee: Adaptec, Inc.
    Inventors: Afshin D. Momtaz, Mario T. Caresosa
  • Patent number: 6205527
    Abstract: Disclosed is an apparatus, a system, a computer readable media, and a method for protecting data of a computer system. The method includes: (a) connecting a peripheral storage device to the computer system; (b) preparing a storage media of the peripheral storage device to be a protection enabled media; (c) selecting a backup set of data stored in a hard drive of the computer system, the backup set of data includes a default set of boot files and operating system files; (d) creating a spare tire backup using file-based copying from the hard drive of the computer system to the storage media of the peripheral storage device; (e) enabling the peripheral storage device to incrementally copy portions of the backup set of data from the hard drive of the computer system during normal use; and (f) booting the computer system from the peripheral storage device when a failure occurs with the hard drive that disables normal booting.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: March 20, 2001
    Assignee: Adaptec, Inc.
    Inventors: Michael M. Goshey, Guido Maffezzoni, Gilbert Chang-Tying Wu, Yen-Chung Lin, John D. Nguyen, Roger A. Stoller, Kristine N. Luong, Robert S. Hudson, David A. Coleman, Dennis M. Sumners, Thanh T. Bui, Tony Fu, Tony G. Kwan
  • Patent number: 6201829
    Abstract: A pseudo-random built in self test pattern generator is constructed of eight sequential D-flip flops and configured to output 10-bit wide pattern data which conforms to the 8B/1OB transmission protocol. The first and fifth D-flip flops of the array have their outputs split, with one leg of the split directly defining a character bit and the other leg of the split defining an inverted character bit. The outputs of the first, second, seventh and eighth D-flip flops are directed to a four input EXOR gate whose output is connected to the D input of the first D-flip flop of the array. Configured as a recirculating feed back loop, the pattern generator defines a sequence of 10-bit patterns in which no more than five sequential 1s or five sequential 0s are generated either within a pattern or on pattern boundaries. The pattern generator provides 255 Fiber Channel-type transmission characters to a Fiber Channel-type transceiver circuit which serializes the characters into a 1.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: March 13, 2001
    Assignee: Adaptec, Inc.
    Inventor: Thomas R. Schneider
  • Patent number: 6200201
    Abstract: A semiconductor processing system, such as a system for buffing or scrubbing both sides of a wafer at the same time, that includes a processing box for use with chemical solutions, a positioning device to position a semiconductor substrate, or other similar semiconductor material or device, and a placement device to place a buffing pad or scrubbing brush.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: March 13, 2001
    Assignee: Lam Research Corporation
    Inventors: Mikhael Ravkin, John M. deLarios, Xiuhua Zhang, Thomas R. Gockel
  • Patent number: 6199194
    Abstract: A method and apparatus for programming a programmable hardware device of a local computer system that is connected to a network, uses a programming file that is resident on a remote system which is also connected to the same network. A method for facilitating such programming includes providing a Java-language program that is capable of accessing a programming file having data, providing a Java Native Interface (JNI) implementation that is capable of facilitating a sending of data from the programming file to the programmable hardware device, and providing a Java Native Interface that facilitates communication between the Java-language program and the JNI implementation. Another method for such programming by a user includes accessing a programming file having data and located on a computer system that is remote from the local system and connected to the local system through a network, using a Java program.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: March 6, 2001
    Assignee: Adaptec, Inc.
    Inventors: Sin-Yaw Wang, Christopher M. Bellman, Elvis Lam
  • Patent number: 6199178
    Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: March 6, 2001
    Assignee: Wild File, Inc.
    Inventors: Eric Schneider, Chuck Ferril, Dough Wheeler, Larry Schwartz, Edward Bruggeman
  • Patent number: 6197673
    Abstract: A method for fabricating a passivation layer of a gate electrode. A conductive layer, a mask layer and a patterned photoresist layer are sequentially formed on a gate oxide layer. The photoresists layer is thick enough to precisely transfer a pattern from the photoresist layer to the mask layer. The photoresist layer is stripped, and an etching step is performed to transfer the patterned of the mask layer onto the conductive layer, so as to form a gate electrode. During the etching step, a corner of the mask layer is partly truncated to form a cap layer with an arc shape corner. A conformal liner oxide layer is formed on the cap layer and a sidewall of the gate electrode. A spacer is further formed on the conformal liner oxide layer extending over a top surface of the gate electrode.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: March 6, 2001
    Assignees: United Semiconductor Corp., United Microelectronics Corp.
    Inventor: Chia-Chieh Yu